Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 12/08/2023
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Datasheet
Intel® Stratix® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Stratix® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications x
Differential POD12 Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications L-Tile Transceiver Performance Specifications H-Tile Transceiver Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Direct Interface Bus (DIB) Specifications Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications Memory Output Clock Jitter Specifications Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices HBM2 Interface Performance OCT Calibration Block Specifications
L-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 L-Tile Devices Transceiver Specifications for Intel® Stratix® 10 L-Tile Devices
H-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 H-Tile Devices Transceiver Specifications for Intel® Stratix® 10 H-Tile Devices
E-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 E-Tile Devices Transceiver Reference Clock Specifications Transmitter Specifications for Intel® Stratix® 10 E-Tile Devices Receiver Specifications for Intel® Stratix® 10 E-Tile Devices
P-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 DX P-Tile Devices Transceiver Reference Clock Specifications Transmitter Specification for Intel® Stratix® 10 DX P-Tile Devices Receiver Specifications for Intel® Stratix® 10 DX P-Tile Devices
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® -ST Configuration Timing Configuration Bit Stream Sizes
Intel® Stratix® 10 Device Datasheet

AS Configuration Timing

Table 103.  AS Timing Parameters for Intel® Stratix® 10 Devices Intel recommends performing trace length matching for nCSO and AS_DATA pins to AS_CLK to minimize the skew. Refer to Stratix 10 Configuration User Guide to calculate the maximum allowable skew tolerance for nCSO and AS_DATA pins to AS_CLK.
Symbol Description Minimum Typical Maximum Unit
Tclk 163 AS_CLK clock period — 8 — ns
Tdutycycle AS_CLK duty cycle 45 50 55 %
Tdcsfrs AS_nCSO[3:0] asserted to first AS_CLK edge 11.65 — — ns
Tdcslst Last AS_CLK edge to AS_nCSO[3:0] deasserted 9.23 — — ns
Tdo 164 AS_DATA[3:0] output delay –1.5 — 1.31 ns
Text_delay 165 166 167 Total external propagation delay on AS signals 0 — 18 ns
Tdcsb2b Minimum delay of slave select deassertion between two back-to-back transfers 62 — — ns
Figure 28. AS Configuration Serial Output Timing Diagram
Figure 29. AS Configuration Serial Input Timing Diagram
Related Information
163 AS_CLK fmax has dependency on the maximum board loading. For AS single device configuration or AS using multiple serial flash devices configuration, use the equations in Tdo and Text_delay notes to ensure your board has sufficient timing margin to meet flash setup/hold time specifications and Intel® Stratix® 10 AS timing specifications in the Intel® Stratix® 10 Device Datasheet. For AS using multiple serial flash devices, refer to the Intel® Stratix® 10 Configuration User Guide for the recommended AS_CLK frequency and maximum board loading.
164

Load capacitance for DCLK = 10 pF and AS_DATA = 18 pF. Intel recommends obtaining the Tdo for a given link (including receiver, transmission lines, connectors, termination resistors, and other components) through IBIS or HSPICE simulation.

Use the following equations to do static timing analysis for flash setup/hold timing.

  • To analyze flash setup time, Tsu = AS_CLK/2 – Tdo(max) + Tbd_clk – Tbd_data(max)
  • To analyze flash hold time, Tho = AS_CLK/2 + Tdo(min) – Tbd_clk + Tbd_data(min)
165

Text_delay = Tbd_clk + Tco + Tbd_data + Tadd

Tbd_clk: Propagation delay for AS_CLK between FPGA and flash device.

Tco: Output hold time and clock low to output valid of flash device. This delay must be used to ensure Text_delay is within the minimum and maximum specification values.

Tbd_data: Propagation delay for AS_DATA bus between FPGA and flash device.

Tadd: Propagation delay for active/passive components on AS_DATA interfaces.

166 Meeting Text_delay timing specifications indicates that the AS_DATA setup/hold timing is met.
167 Text_delay specification is based on AS_CLK = 125 MHz. The value can be larger at lower AS_CLK frequency. For more details, refer to the Intel® Stratix® 10 Configuration User Guide.
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