Intel® Stratix® 10 Device Datasheet

ID 683181
Date 1/12/2022
Document Table of Contents

AS Configuration Timing

Table 102.  AS Timing Parameters for Intel® Stratix® 10 Devices Intel recommends performing trace length matching for nCSO and AS_DATA pins to AS_CLK to minimize the skew. The maximum tolerance for skew between nCSO and AS_CLK is recommended to be less than 200 ps. The tolerance for skew between AS_CLK to AS_DATA must be within 0 ps – 400 ps.
Symbol Description Minimum Typical Maximum Unit
Tclk 166 AS_CLK clock period 8 ns
Tdutycycle AS_CLK duty cycle 45 50 55 %
Tdcsfrs AS_nCSO[3:0] asserted to first AS_CLK edge 11.65 ns
Tdcslst Last AS_CLK edge to AS_nCSO[3:0] deasserted 9.23 ns
Tdo 167 AS_DATA[3:0] output delay –1.5 1.31 ns
Text_delay 168 169 170 Total external propagation delay on AS signals 0 18 ns
Tdcsb2b Minimum delay of slave select deassertion between two back-to-back transfers 62 ns
Figure 27. AS Configuration Serial Output Timing Diagram
Figure 28. AS Configuration Serial Input Timing Diagram
166 AS_CLK fmax has dependency on the maximum board loading. For AS single device configuration or AS using multiple serial flash devices configuration, use the equations in Tdo and Text_delay notes to ensure your board has sufficient timing margin to meet flash setup/hold time specifications and Intel® Stratix® 10 AS timing specifications in the Intel® Stratix® 10 Device Datasheet. For AS using multiple serial flash devices, refer to the Intel® Stratix® 10 Configuration User Guide for the recommended AS_CLK frequency and maximum board loading.

Load capacitance for DCLK = 10 pF and AS_DATA = 18 pF. Intel recommends obtaining the Tdo for a given link (including receiver, transmission lines, connectors, termination resistors, and other components) through IBIS or HSPICE simulation.

Use the following equations to do static timing analysis for flash setup/hold timing.

  • To analyze flash setup time, Tsu = AS_CLK/2 – Tdo(max) + Tbd_clk – Tbd_data(max)
  • To analyze flash hold time, Tho = AS_CLK/2 + Tdo(min) – Tbd_clk + Tbd_data(min)

Text_delay = Tbd_clk + Tco + Tbd_data + Tadd

Tbd_clk: Propagation delay for AS_CLK between FPGA and flash device.

Tco: Output hold time and clock low to output valid of flash device. This delay must be used to ensure Text_delay is within the minimum and maximum specification values.

Tbd_data: Propagation delay for AS_DATA bus between FPGA and flash device.

Tadd: Propagation delay for active/passive components on AS_DATA interfaces.

169 Meeting Text_delay timing specifications indicates that the AS_DATA setup/hold timing is met.
170 Text_delay specification is based on AS_CLK = 125 MHz. The value can be larger at lower AS_CLK frequency. For more details, refer to the Intel® Stratix® 10 Configuration User Guide.

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