Intel® Stratix® 10 Device Datasheet

ID 683181
Date 1/12/2022
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I/O PLL Specifications

Table 29.  I/O PLL Specifications for Intel® Stratix® 10 Devices
Symbol Parameter Condition Min Typ Max Unit
fIN Input clock frequency –1 speed grade 10 1,100 49 MHz
–2 speed grade 10 900 49 MHz
–3 speed grade 10 750 49 MHz
fINPFD Input clock frequency to the PFD 10 325 MHz
fVCO PLL VCO operating range –1 speed grade 600 1,600 MHz
–2 speed grade 600 1,434 MHz
–3 speed grade 600 1,280 50 MHz
fCLBW PLL closed-loop bandwidth 0.5 10 MHz
tEINDUTY Input clock or external feedback clock input duty cycle 40 60 %
fOUT Output frequency for internal clock (C counter) –1 speed grade 1,100 MHz
–2 speed grade 900 MHz
–3 speed grade 750 MHz
fOUT_EXT Output frequency for external clock output –1 speed grade 800 MHz
–2 speed grade 720 MHz
–3 speed grade 650 MHz
tOUTDUTY Duty cycle for dedicated external clock output (when set to 50%) 45 50 55 %
tFCOMP External feedback clock compensation time 5 ns
fDYCONFIGCLK Dynamic configuration clock for mgmt_clk and scanclk 200 MHz
tLOCK Time required to lock from end-of-device configuration or deassertion of areset 1 ms
tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) 1 ms
tPLL_PSERR Accuracy of PLL phase shift ±50 ps
tARESET Minimum pulse width on the areset signal 10 ns
tINCCJ 51 52 Input clock cycle-to-cycle jitter FREF ≥ 100 MHz 0.15 UI (p-p)
FREF < 100 MHz ±750 ps (p-p)
tOUTPJ_DC Period jitter for dedicated clock output FOUT ≥ 100 MHz 175 ps (p-p)
FOUT < 100 MHz 17.5 mUI (p-p)
tOUTCCJ_DC Cycle-to-cycle jitter for dedicated clock output FOUT ≥ 100 MHz 175 ps (p-p)
FOUT < 100 MHz 17.5 mUI (p-p)
tOUTPJ_IO 53 Period jitter for clock output on the regular I/O FOUT ≥ 100 MHz 600 ps (p-p)
FOUT < 100 MHz 60 mUI (p-p)
tOUTCCJ_IO 53 Cycle-to-cycle jitter for clock output on the regular I/O FOUT ≥ 100 MHz 600 ps (p-p)
FOUT < 100 MHz 60 mUI (p-p)
tCASC_OUTPJ_DC Period jitter for dedicated clock output in cascaded PLLs through dedicated cascade path and core clock fabric FOUT ≥ 100 MHz 175 ps (p-p)
FOUT < 100 MHz 17.5 mUI (p-p)
49 This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
50 This specification is only applicable when the I/O PLL is instantiated with the IOPLL Intel® FPGA IP core. For I/O PLL instantiated with LVDS SERDES Intel® FPGA IP core, PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP core, External Memory Interfaces Intel Stratix 10 FPGA IP core, and High Bandwidth Memory (HBM-2) Interface Intel® FPGA IP core, the maximum fVCO is 1,250 MHz.
51  A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
52 FREF is fIN/N, specification applies when N = 1.
53 External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specifications for Intel® Stratix® 10 Devices table.

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