Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 1/12/2022
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HPS NAND Timing Characteristics

Table 94.  HPS NAND ONFI 1.0 Timing Requirements for Intel® Stratix® 10 Devices
Symbol Description Min Max Unit
TWP 162 Write enable pulse width 10 ns
TWH 162 Write enable hold time 7 ns
TRP 162 Read enable pulse width 10 ns
TREH 162 Read enable hold time 7 ns
TCLS 162 Command latch enable to write enable setup time 10 ns
TCLH 162 Command latch enable to write enable hold time 5 ns
TCS 162 Chip enable to write enable setup time 15 ns
TCH 162 Chip enable to write enable hold time 5 ns
TALS 162 Address latch enable to write enable setup time 10 ns
TALH 162 Address latch enable to write enable hold time 5 ns
TDS 162 Data to write enable setup time 7 ns
TDH 162 Data to write enable hold time 5 ns
TWB 162 Write enable high to R/B low 200 ns
TCEA Chip enable to data access time 100 ns
TREA Read enable to data access time 40 ns
TRHZ Read enable to data high impedance 200 ns
TRR Ready to read enable low 20 ns
Figure 17. NAND Command Latch Timing Diagram
Figure 18. NAND Address Latch Timing Diagram
Figure 19. NAND Data Output Cycle Timing Diagram
Figure 20. NAND Data Input Cycle Timing Diagram
Figure 21. NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle
Figure 22. NAND Read Status Timing Diagram
Figure 23. NAND Read Status Enhanced Timing Diagram
162 This timing is software programmable. Refer to the NAND Flash Controller chapter in the Stratix 10 Hard Processor System Technical Reference Manual for more information about software-programmable timing in the NAND flash controller.

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