Intel® Stratix® 10 Device Datasheet

ID 683181
Date 1/12/2022
Document Table of Contents

JTAG Configuration Timing

Table 101.  JTAG Timing Parameters and Values for Intel® Stratix® 10 Devices
Symbol Description Requirement Unit
Minimum Maximum
tJCP TCK clock period 30 ns
tJCH TCK clock high time 14 ns
tJCL TCK clock low time 14 ns
tJPSU (TDI) TDI JTAG port setup time 2 ns
tJPSU (TMS) TMS JTAG port setup time 3 ns
tJPH JTAG port hold time 5 ns
tJPCO JTAG port clock to output 7 ns
tJPZX JTAG port high impedance to valid output 14 ns
tJPXZ JTAG port valid output to high impedance 14 ns
Note: P-tile supports IEEE 1149.6 JTAG standard at maximum speed of 1 MHz only if you use EXTEST_PULSE/EXTEST_TRAIN AC JTAG instruction.
Figure 26. JTAG Timing Diagram

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