Intel® Stratix® 10 Device Datasheet

ID 683181
Date 1/12/2022
Document Table of Contents

HPS USB UPLI Timing Characteristics

Table 86.  HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for Intel® Stratix® 10 Devices
Symbol Description Min Typ Max Unit
Tusb_clk USB_CLK clock period 16.667 ns
Td Clock to USB_STP/USB_DATA[7:0] output delay 2 7 ns
Tsu Setup time for USB_DIR/USB_NXT/USB_DATA[7:0] 4 ns
Th Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] 1 ns
Figure 12. USB ULPI Timing Diagram
Note: The USB interface supports single data rate (SDR) timing only.

Did you find the information on this page useful?

Characters remaining:

Feedback Message