Intel® Stratix® 10 Device Datasheet

ID 683181
Date 1/12/2022
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Programmable IOE Delay

Table 105.  Programmable IOE Delay for Intel® Stratix® 10 Devices

For the exact values for each setting, use the latest version of the Intel® Quartus® Prime software. The values in the table show the delay of programmable IOE delay chain with maximum offset settings after excluding the intrinsic delay (delay at minimum offset settings).

Programmable IOE delay settings are only applicable for I/O buffers and do not apply for any other delay elements in the PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP core.

Parameter 173 Maximum Offset Minimum Offset 174 Fast Model Slow Model Unit
Industrial/Extended –E1V, –I1V –E2V, –I2V –E3V, –I3V
Input Delay Chain ( INPUT_DELAY_CHAIN ) 63 0 1.575 2.310 2.352 2.654 ns
Output Delay Chain ( OUTPUT_DELAY_CHAIN ) 15 0 0.387 0.523 0.560 0.629 ns
173 You can set this value in the Intel® Quartus® Prime software by selecting Input Delay Chain Setting or Output Delay Chain Setting in the Assignment Name column.
174 Minimum offset does not include the intrinsic delay.

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