Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 1/12/2022
Public
Document Table of Contents

Transceiver Performance for Intel® Stratix® 10 DX P-Tile Devices

Table 72.  P-Tile Transmitter and Receiver Data Rate Performance For specification status, see the Data Sheet Status table
Symbol/Description Condition Gen 1 Gen 2 Gen 3 Gen 4 Unit
Supported data rate126 PCIe* 2.5 5 8 16 Gbps
Table 73.  P-Tile PLLA Performance For specification status, see the Data Sheet Status table
Symbol/Description Condition Min Typ Max Unit
VCO frequency PCIe* 5 GHz
Intel® UPI 127 5.2 GHz
PLL bandwidth (BWTX_PKG_PLL1) 128 PCIe* 2.5 GT/s 1.5 22 MHz
PCIe* 5.0 GT/s 8 16 MHz
PLL bandwidth (BWTX_PKG_PLL2)128 PCIe* 5.0 GT/s 5 16 MHz
PLL peaking (PKGTX_PLL1) PCIe* 2.5 GT/s 3 dB
PCIe* 5.0 GT/s 3 dB
PLL peaking (PKGTX_PLL2)128 PCIe* 5.0 GT/s 1 dB
Table 74.  P-Tile PLLB Performance For specification status, see the Data Sheet Status table. PLLB is not used for the UPI mode.
Symbol/Description Condition Min Typ Max Unit
VCO frequency PCIe* 8 GHz
PLL bandwidth (BWTX-PKG_PLL1) 129 PCIe* 8.0 GT/s 2 4 MHz
PCIe* 16.0 GT/s 2 4 MHz
PLL bandwidth (BWTX-PKG_PLL2)129 PCIe* 8.0 GT/s 2 5 MHz
PCIe* 16.0 GT/s 2 5 MHz
PLL peaking (PKGTX-PLL1)129 PCIe* 8.0 GT/s 2 dB
PCIe* 16.0 GT/s 2 dB
PLL peaking (PKGTX-PLL2)129 PCIe* 8.0 GT/s 1 dB
PCIe* 16.0 GT/s 1 dB
126 Intel® Ultra Path Interconnect ( Intel® UPI) supports chip-to-chip and low-loss cable up to 10.4 Gbps.
127 The maximum VCO frequency supported now for PLLA in Intel® UPI mode is 5.2 GHz. This will increase to 5.6 GHz in future for Intel® UPI mode operating at 11.2 Gbps.
128 The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at the point where its transfer function crosses the –3 dB point.
129 The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at the point where its transfer function crosses the –3 dB point.

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