Intel® Stratix® 10 Device Datasheet

ID 683181
Date 12/08/2023
Public
Document Table of Contents

Transceiver Performance for Intel® Stratix® 10 DX P-Tile Devices

Table 73.  P-Tile Transmitter and Receiver Data Rate Performance For specification status, see the Data Sheet Status table
Symbol/Description Condition Gen 1 Gen 2 Gen 3 Gen 4 Unit
Supported data rate124 PCIe* 2.5 5 8 16 Gbps
Table 74.  P-Tile PLLA Performance For specification status, see the Data Sheet Status table
Symbol/Description Condition Min Typ Max Unit
VCO frequency PCIe* 5 GHz
Intel® UPI uwk1553212023175.html#uwk1553212023175__fn_apll-f1 5.2 GHz
PLL bandwidth (BWTX_PKG_PLL1) 125 PCIe* 2.5 GT/s 1.5 22 MHz
PCIe* 5.0 GT/s 8 16 MHz
PLL bandwidth (BWTX_PKG_PLL2)125 PCIe* 5.0 GT/s 5 16 MHz
PLL peaking (PKGTX_PLL1) PCIe* 2.5 GT/s 3 dB
PCIe* 5.0 GT/s 3 dB
PLL peaking (PKGTX_PLL2)125 PCIe* 5.0 GT/s 1 dB
Table 75.  P-Tile PLLB Performance For specification status, see the Data Sheet Status table. PLLB is not used for the UPI mode.
Symbol/Description Condition Min Typ Max Unit
VCO frequency PCIe* 8 GHz
PLL bandwidth (BWTX-PKG_PLL1) 126 PCIe* 8.0 GT/s 2 4 MHz
PCIe* 16.0 GT/s 2 4 MHz
PLL bandwidth (BWTX-PKG_PLL2)126 PCIe* 8.0 GT/s 2 5 MHz
PCIe* 16.0 GT/s 2 5 MHz
PLL peaking (PKGTX-PLL1)126 PCIe* 8.0 GT/s 2 dB
PCIe* 16.0 GT/s 2 dB
PLL peaking (PKGTX-PLL2)126 PCIe* 8.0 GT/s 1 dB
PCIe* 16.0 GT/s 1 dB
124 Intel® Ultra Path Interconnect ( Intel® UPI) supports chip-to-chip and low-loss cable up to 10.4 Gbps.
125 The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at the point where its transfer function crosses the –3 dB point.
126 The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at the point where its transfer function crosses the –3 dB point.