Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 1/12/2022
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HPS Clock Performance

Table 78.  Maximum HPS Clock Frequencies for Intel® Stratix® 10 Devices
Performance VCCL_HPS (V) MPU Frequency (MHz) SDRAM Interconnect Frequency138 (MHz) L3 Interconnect Frequency (MHz)
–E1V, –I1V SmartVID 1,200 533 400
0.9 1,200 533 400
0.94 1,350 533 400 139
–E2V, –I2V SmartVID 1,000 467 400
0.9 1,000 467 400
0.94 1,000 467 400
–E3V, –I3V SmartVID 800 400 333
0.9 800 400 333
0.94 800 400 400
–E2L, –I2L 140 0.9 1200 467 400
0.94 1,350 467 400 139
–E3X, –I3X 140 0.9 1,200 400 400
0.94 1,350 400 400 139
138 This frequency is for the hmc_free_clk, which is half the frequency of the HPS external memory interface (EMIF).
139 If MPU frequency is 1,350 MHz, the L3 interconnect frequency is 385 MHz because of the clock ratios.
140

Note that VCCL_HPS can not be connected to SmartVID for –E2L, –I2L, –E3X, and –I3X devices.

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