Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications Memory Output Clock Jitter Specifications Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices HBM2 Interface Performance OCT Calibration Block Specifications
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
HPS Clock Performance
|Performance||VCCL_HPS (V)||MPU Frequency (MHz)||SDRAM Interconnect Frequency138 (MHz)||L3 Interconnect Frequency (MHz)|
|–E2L, –I2L 140||0.9||1200||467||400|
|–E3X, –I3X 140||0.9||1,200||400||400|
138 This frequency is for the hmc_free_clk, which is half the frequency of the HPS external memory interface (EMIF).
139 If MPU frequency is 1,350 MHz, the L3 interconnect frequency is 385 MHz because of the clock ratios.
Note that VCCL_HPS can not be connected to SmartVID for –E2L, –I2L, –E3X, and –I3X devices.
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