Intel® Stratix® 10 Device Datasheet

ID 683181
Date 1/12/2022
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Transceiver Reference Clock Specifications

Table 68.  E-Tile Reference Clock LVPECL DC Electrical Characteristics
Symbol Refclk Parameter Minimum Typical Maximum Unit
VTT Termination Voltage (2.5V compliant) 0.4 0.5 0.6 V
VTT Termination Voltage (3.3V compliant) 1.04 1.3 1.56 V
RTT Termination Resistor 40 50 60 Ohm
VDIFF Differential Voltage 0.4 0.8 1.2 V
VCM Input Common Mode Voltage (2.5V compliant, no internal termination resistor) VDIFF/2   VCCCLK_GXE-VDIFF/2 V
VCM Input Common Mode Voltage (2.5V compliant, internal termination resistor) VCCCLK_GXE - 1.6 VCCCLK_GXE - 1.3 VCCCLK_GXE - 1.0 V
VCM Input Common Mode Voltage (3.3V compliant, no internal termination resistor) VDIFF/2   VCCCLK_GXE-VDIFF/2 V
VCM Input Common Mode Voltage (3.3V compliant, internal termination resistor) 1.4 2 2.6 V
Table 69.  E-Tile Reference Clock Electrical & Jitter Requirements
Parameter Condition Minimum Typical Maximum Unit
Frequency - 125 156.25 700 MHz
Frequency Tolerance - -100   100 PPM
Clock Duty Cycle - 45 50 55 %
Rise & Fall Times 20% - 80% 40   300 ps
Phase Jitter 12 KHz - 20 MHz   0.375 0.5 ps rms
Phase Noise 121 10 KHz     -130 dBc/Hz
100 KHz     -138 dBc/Hz
500 KHz     -138 dBc/Hz
3 MHz     -140 dBc/Hz
10 MHz     -144 dBc/Hz
20 MHz     -146 dBc/Hz
121 The phase noise numbers in the table above are the maximum acceptable phase noise values measured at a carrier frequency of 156.25 MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 156.25 MHz + 20*log10(f/156.25)

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