Intel® Stratix® 10 Device Datasheet

ID 683181
Date 12/08/2023
Document Table of Contents

Memory Output Clock Jitter Specifications

The clock jitter specification applies to the memory output clock pins clocked by an I/O PLL, or generated using differential signal-splitter and double data I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Intel recommends using PHY clock networks for better jitter performance.

The memory clock output jitter is within the JEDEC* specifications with an input of 10 ps peak-to-peak jitter.