Intel® Stratix® 10 Device Datasheet

ID 683181
Date 1/12/2022
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OCT Without Calibration Resistance Tolerance Specifications

Table 18.  OCT Without Calibration Resistance Tolerance Specifications for Intel® Stratix® 10 DevicesThis table lists the Intel® Stratix® 10 OCT without calibration resistance tolerance to PVT changes.
Symbol Description I/O Buffer Type Condition (V) Resistance Tolerance Unit
–E1, –I1 –E2, –I2 –E3, –I3
25-Ω and 50-Ω RS Internal series termination without calibration
(25-Ω and 50-Ω setting) 3 V I/O VCCIO = 3.0, 2.5, 1.8, 1.5, 1.2 –40 to +30 ±40 ±40 %
25-Ω and 50-Ω RS Internal series termination without calibration
(25-Ω and 50-Ω setting) LVDS I/O VCCIO = 1.8, 1.5, 1.2 –20 to +35 –20 to +35 –20 to +35 %
34-Ω and 40-Ω RS Internal series termination without calibration
(34-Ω and 40-Ω setting) LVDS I/O VCCIO = 1.5, 1.35, 1.25, 1.2 –20 to +35 –20 to +35 –20 to +35 %
48-Ω, 60-Ω, 80-Ω, and 240-Ω RS Internal series termination without calibration
(48-Ω, 60-Ω, 80-Ω, and 240-Ω setting) LVDS I/O VCCIO = 1.2 –20 to +35 –20 to +35 –20 to +35 %
100-Ω RD Internal differential termination (100-Ω setting) LVDS I/O VCCIO = 1.8 ±25 ±35 ±40 %

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