Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications Memory Output Clock Jitter Specifications Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices HBM2 Interface Performance OCT Calibration Block Specifications
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
General Configuration Timing Specifications
|tCF12ST1||nCONFIG high to nSTATUS high||—||20||ms|
|tCF02ST0||nCONFIG low to nSTATUS low when device is configured||—||400 163||ms|
|tST0||nSTATUS low pulse during configuration error||0.5||10||ms|
|tCD2UM 164||CONF_DONE high to user mode||—||5||ms|
|tST12CF0||Minimum time to drive nCONFIG from high to low after nSTATUS transitions from low to high||0||—||ms|
|tST02CF1||Minimum time to drive nCONFIG from low to high after nSTATUS transitions from high to low||0||—||ms|
Figure 25. General Configuration Timing Diagram
163 The duration may be up to 1000 ms if using device security feature.
164 This specification is the initialization time that indicates the time from CONF_DONE signal goes high to INIT_DONE signal goes high.
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