Intel® Stratix® 10 Device Datasheet

ID 683181
Date 1/12/2022
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Transceiver Performance for Intel® Stratix® 10 GX/SX/MX/TX H-Tile Devices

Table 56.   Intel® Stratix® 10 GX/SX/MX/TX H-Tile Transmitter and Receiver Datarate Performance
Symbol Description Transceiver Speed Grade
-1 -2 -3
GX channels Chip-to-chip and Backplane 17.4 Gbps
GXT channels Chip-to-chip and Backplane 28.3 Gbps 96 26.6 Gbps N/A
Note: Refer to the Transceiver Power Supply Operating Conditions for VCCR_GXB and VCCT_GXB specifications when using bonded and non-bonded transceiver channels in Intel® Stratix® 10 H-Tile devices.
Table 57.  H-Tile ATX PLL Performance
Symbol/Description Condition Transceiver Speed Grade 1 Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit
Supported Output Frequency Maximum Frequency 14.15 13.3 8.7 GHz
Minimum Frequency 500 MHz
tLOCK 97 Maximum Frequency 1 ms
tARESET 98 25 Avalon Clock Cycles
Note: TX jitter specifications for the SerialLite III protocol at 17.4 Gbps are as low as: TJ = 0.32 UI, RJ = 0.15 UI, DJ = 0.18 UI, and DCD = 0.05 UI.
Table 58.  H-Tile Fractional PLL Performance
Symbol/Description Condition Mode All Transceiver Speed Grades Unit
Supported Output Frequency (VCO frequency based) Maximum datarate Transceiver - HDMI 12.5 Gbps
Transceiver - General 12.5
Transceiver - OTN, SDI Cascade 14.025
Minimum datarate Transceiver - HDMI 4.6 Gbps
Transceiver - General 6
Transceiver - OTN, SDI Cascade 7
tLOCK 97 Maximum Frequency   1 ms
tARESET 98   25 Avalon Clock Cycles
Table 59.  H-Tile CMU PLL Performance
Symbol/Description Condition All Transceiver Speed Grades Unit
Supported Output Frequency Maximum Frequency 5.15625 GHz
Minimum Frequency 2.450 GHz
tLOCK 97 Maximum Frequency 1 ms
tARESET 98 25 Avalon Clock Cycles
96 Only four GXT channels per bank are supported for backplane applications operating at 28.3 Gbps.
97 This specification applies after the ATX PLL, fPLL, or CMU PLL has completed calibration.
98 You must use the Avalon-MM interface to hold the PLLs in reset for the specified cycles by writing to the ATX PLL, fPLL, or CMU PLL pll_powerdown register.

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