Intel® Stratix® 10 Device Datasheet

ID 683181
Date 12/08/2023
Document Table of Contents

OCT Calibration Block Specifications

Table 45.  OCT Calibration Block Specifications for Intel® Stratix® 10 Devices
Symbol Description Min Typ Max Unit
OCTUSRCLK Clock required by OCT calibration blocks 20 MHz
TOCTCAL Number of OCTUSRCLK clock cycles required for
RS OCT /RT OCT calibration > 2000 Cycles
TOCTSHIFT Number of OCTUSRCLK clock cycles required for OCT code to shift out 32 Cycles
TRS_RT Time required between the dyn_term_ctrl and oe signal transitions in a bidirectional I/O buffer to dynamically switch between RS OCT and RT OCT 8 Full-rate cycle
Figure 6. Timing Diagram for on oe and dyn_term_ctrl Signals