L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 10/05/2023
Document Table of Contents

5.8. PRBS Pattern Verifier

You can use the PRBS pattern verifier to easily characterize high-speed links.

The PRBS Pattern Verifier supports 5 modes:
  • PRBS7
  • PRBS9
  • PRBS15
  • PRBS23
  • PRBS31
Figure 228. PRBS9 Verify Serial Implementation

The PRBS verifier has the following control and status signals available to the FPGA fabric:

  • rx_prbs_done—Indicates the PRBS sequence has completed one full cycle. It stays high until you reset it with rx_prbs_err_clr.
  • rx_prbs_err—Goes high if an error occurs. This signal is pulse-extended to allow you to capture it in the RX FPGA CLK domain.
  • rx_prbs_err_clr—Used to reset the rx_prbs_err signal.

Enable the PRBS verifier control and status ports through the Native PHY IP core.