L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Document Table of Contents

6. Reconfiguration Interface and Dynamic Reconfiguration

This chapter explains the purpose and the use of the Intel® Stratix® 10 reconfiguration interface that is part of the Transceiver Native PHY IP core and the Transceiver PLL IP cores.
Dynamic reconfiguration is the process of modifying transceiver channels and PLLs to meet changing requirements during device operation. You can customize channels and PLLs by triggering reconfiguration during device operation or following power-up. Dynamic reconfiguration is available for Intel® Stratix® 10 L-Tile/H-Tile Transceiver Native PHY, fPLL, ATX PLL, and CMU PLL IP cores.
Note: In Intel® Stratix® 10, the Embedded Multi-die Interconnect Bridge (EMIB) must also be reconfigured in addition to channels and PLLs using the reconfiguration interface.
Figure 232. Reconfigurable Interfaces

Use the reconfiguration interface to dynamically change the transceiver channel or PLL settings, EMIB settings for the following applications:

  • Fine tuning signal integrity by adjusting TX and RX analog settings
  • Enabling or disabling transceiver channel blocks, such as the PRBS generator and the verifier
  • Changing data rates to perform auto negotiation in CPRI, SATA, or SAS applications
  • Changing data rates in Ethernet (1G/10G) applications by switching between standard and enhanced PCS datapaths
  • Changing TX PLL settings for multi-data rate support protocols such as CPRI
  • Changing RX CDR settings from one data rate to another
  • Switching between multiple TX PLLs for multi-data rate support

The Native PHY and Transmit PLL IP cores provide the following features that allow dynamic reconfiguration:

  • Reconfiguration interface
  • Configuration files
  • Multiple reconfiguration profiles
  • Embedded reconfiguration streamer
  • Native PHY Debug Master Endpoint (NPDME)
  • Optional reconfiguration logic