L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.4.2.5.1. Enhanced PCS FIFO Operation

Phase Compensation Mode

Phase compensation mode ensures correct data transfer between the core clock and parallel clock domains. The read and write sides of the TX Core or RX Core FIFO must be driven by the same clock frequency. The depth of the TX or RX FIFO is constant in this mode. Therefore, the TX Core or RX Core FIFO flag status can be ignored. You can tie tx_fifo_wr_en or rx_data_valid to logic level 1.

Basic Mode

Basic mode allows you to drive the write and read side of a FIFO with different clock frequencies. tx_coreclkin or rx_coreclkin must have a minimum frequency of the lane datarate divided by 66. The frequency range for tx_coreclkin or rx_coreclkin is (datarate/32) to (datarate/66). For best results, Intel recommends that tx_coreclkin or rx_coreclkin be set to (datarate/32). Monitor the FIFO flag to control write and read operations.

For TX FIFO, assert tx_enh_data_valid with the tx_fifo_pfull signal going low. This can be done with the following example assignment:

assign tx_enh_data_valid = ~tx_fifo_pfull;  
Figure 64. TX FIFO Basic Mode Operation

For RX FIFO, assert rx_enh_read_en with the rx_fifo_pempty signal going low. This can be done with the following example assignment:

assign rx_enh_read_en = ~rx_fifo_pempty;
Figure 65. RX FIFO Basic Mode Operation

If you are using a 1:1 gear ratio, the rx_enh_data_valid signal is always high, so you must use the rx_data_valid signal to determine if the RX parallel data is valid.

On the other hand, if you are using a gear ratio that is not 1:1 such as 66:40 or 64:32, rx_enh_data_valid switches between high and low, so:

  • The RX parallel data is valid when rx_enh_data_valid is high.
  • And you must discard the invalid RX parallel data when rx_enh_data_valid is low.

Register Mode

In this mode, the FIFO is bypassed. The read and the write clock are the same.

10GBASE-R Configurations

In the 10GBASE-R configuration, the TX FIFO behaves as a phase compensation FIFO and the RX FIFO behaves as a clock compensation FIFO.

In the 10GBASE-R with 1588 configuration, both the TX FIFO and the RX FIFO are used in phase compensation mode. The TX and RX phase compensation FIFOs are constructed in the FPGA fabric by the PHY IP automatically.

In the 10GBASE-R with KR FEC configuration, use the TX FIFO in phase compensation mode and the RX FIFO behaves as a clock compensation FIFO.

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