L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.4.2.12.2. How to Enable Low Latency in Basic (Enhanced PCS)

In the Native PHY IP Core, use the following settings to enable low latency:

  1. Select the Enable 'Enhanced PCS' low latency mode option.
  2. Select one of the following gear ratios:
    32:32, 40:40, 64:64, 40:64, 32:64, 64:66
  3. Select Phase compensation from the TX Core Interface FIFO mode and RX PCS-Core Interface FIFO mode (PCS FIFO-Core FIFO) pull-down menus.
  4. Enable the tx_clkout2 and rx_clkout2 ports.
  5. Select PCS clkout in the Selected tx_clkout source and Selected rx_clkout source fields.
  6. Select PCS clkout in the Selected tx_clkout2 source and Selected rx_clkout2 source fields.

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