L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

6.6.2. PLL Reconfiguration

  1. For CMU PLL and CDR reconfiguration, if you have background calibration enabled, disable it by setting channel offset address 0x542[0] to 0x0. Skip this step if you are reconfiguring the ATX PLL or fPLL.
    You disabled it successfully if 0x542[0] = 0x0, 0x481[2] = 0x0, or reconfig_waitrequest is low.
  2. Pause Traffic: Assert the required channel resets (if necessary). Refer to the section Recommendations for Dynamic Reconfiguration for details on which resets need to be asserted.
  3. Prepare PLL: Request PreSICE to configure (set pre_reconfig bit ) the fPLL/ATX PLL/CMU PLL/CDR in preparation for reconfiguration. To request PreSICE, read modify write to address 0x100, to modify pre_reconfig bit to value 1 for the fPLL/ATX PLL/CMU PLL/CDR.
    • 1’b1: Request PreSICE to configure the fPLL/ATX PLL/CMU PLL/CDR in reconfiguration mode.
    • 1'b0: Reconfiguration mode not requested.
    Table 158.   pre_reconfig bitmapping
    TX PLL Offset[bit]
    ATX_PLL 0x100[1]
    fPLL 0x100[0]
    CMU PLL/CDR 0x100[3]
  4. Return Control: Return the internal configuration bus access to PreSICE. To return control, direct write at address 0x000 with value 0x01 for fPLL/ATX PLL/CMU PLL/CDR. Wait for PreSICE to complete operation by monitoring the pll_cal_busy/rx_cal_busy signal or reading the pll_cal_busy/rx_cal_busy signal status from the status registers.
  5. Modify: Perform the necessary reconfiguration using the flow described in Direct Reconfiguration Flow, Native PHY or PLL IP Guided Reconfiguration Flow, and Reconfiguration Flow for Special Cases.
  6. Re-align: Request recalibration, if reconfiguration involved data rate or protocol mode change, and wait for the calibration to complete. Calibration is complete when tx/rx/pll_cal_busy is deasserted. For more details about calibration registers and the steps to perform recalibration, refer to the Calibration chapter. If you reconfigured PLL for data rate change—you must recalibrate the PLL and the channel TX.
  7. Return Control: After you have performed all necessary reconfiguration and recalibration, return the internal configuration bus access to PreSICE. To return bus arbitration, direct write 0x01 to offset address 0x000. You may have to reconfigure the PMA analog parameters of the channels. Refer to Changing PMA Analog Parameters for more details.
  8. Resume Traffic: Deassert analog resets followed by digital resets. Refer to "Recommendations for Dynamic Reconfiguration" for details on the resets that needs to be deasserted.
  9. For CMU PLL and CDR reconfiguration and if desired, enable background calibration by setting channel offset address 0x542[0] to 0x1. Skip this step if you are reconfiguring the ATX PLL or fPLL.
    • The background calibration feature is only available for H-tile production devices starting with Intel® Quartus® Prime Design Suite 18.1 and if the data rate is >= 17.5 Gbps.
    • Refer to Background Calibration for more information.

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