L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.4.2.9.2. Receiver Byte Reversal

This is a function of the word alignment block available in the Standard PCS.

You can enable the RX byte reversal feature in Basic/Custom (Standard PCS), Basic/Custom w/ Rate Match (Standard PCS) and in Standard PCS low latency mode.

To enable this feature, select the Enable RX byte reversal and Enable rx_std_byterev_ena port options. This adds rx_std_byterev_ena. If there is more than one channel in the design, rx_std_byterev_ena becomes a bus in which each bit corresponds to a channel. As long as rx_std_byterev_ena is asserted, the RX data received by the core shows byte reversal.

You can verify this feature by monitoring rx_parallel_data.

Figure 80. RX Byte Reversal

You can implement soft logic to perform byte reversal for the Enhanced PCS.

Refer to the Word Aligner RX Byte Reversal Feature section for more information.

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