L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 10/05/2023
Document Table of Contents

7. Calibration

Transceivers include both analog and digital blocks that require calibration to compensate for process, voltage, and temperature (PVT) variations. Intel® Stratix® 10 transceivers use hardened Precision Signal Integrity Calibration Engine (PreSICE) to perform calibration routines. Each transceiver tile has a PreSICE engine. If you are using more than 24 transceiver channels in your design, the transceiver calibrates on a per tile basis. This means that channel 0 in tile 1 and channel 0 in tile 2 are calibrated concurrently, etc.

Power-up Calibration, Background Calibration and User Recalibration are the main types of calibration.

  • Power-up calibration occurs automatically at device power-up. It runs during device configuration.
  • After you enable background calibration, background calibration continuously runs in the background.
  • Use dynamic reconfiguration to trigger user recalibration. In this case, you are responsible for enabling the required calibration sequence.
Note: Only H-Tile production devices support background calibration.

When you upgrade from a previous version of the Intel® Quartus® Prime software to Intel® Quartus® Prime software version 18.1 or above, the Native PHY IP automatically upgrades any H-tile GXT design transceiver link operating at datarates ≥ 17.5 Gbps to Enable background calibration. Refer to Background Calibration for more information about specific requirements and how to control the background calibration.

Intel® Stratix® 10 devices use the OSC_CLK_1 pin to provide the transceiver calibration clock source. You must provide a 25, 100, or 125 MHz free running and stable clock to OSC_CLK_1.

The FPGA's Internal Oscillator cannot be used for transceiver calibration. Do not select this clock source as the Configuration clock source in the Intel® Quartus® Prime settings.

In addition to providing this clock, you must also choose the appropriate frequency in Quartus assignments:

Quartus assignments > Device > Device and Pin Options > Configuration clock source
  1. Scroll down menu
  2. Choose 25, 100, or 125 MHz OSC_CLK_1 pin option.
Figure 250. Calibration Clock Options

You see the selected clock source in .qsf as follows:

set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHz

There is a PLL inside the FPGA that receives the clock from OSC_CLK_1 and provides a 250-MHz calibration clock to PreSICE. All reference clocks driving transceiver PLLs (ATX PLL, fPLL, CDR/CMU PLL) must have a stable frequency and be free running before the start of FPGA configuration (pull the FPGA’s nCONFIG input high). For more information about OSC_CLK_1 pin requirements, refer to the Intel® Stratix® 10 GX and SX Device Family Pin Connection Guidelines.