L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

5.4. Intel® Stratix® 10 PCI Express Gen3 PCS Architecture

Intel® Stratix® 10 architecture supports the PCIe Gen3 specification. Intel provides two options to implement the PCI Express solution:

  • You can use the Intel Hard IP solution. This complete package provides both the MAC layer and the physical (PHY) layer functionality.
  • You can implement the MAC in the FPGA core and connect this MAC to the transceiver PHY through the PIPE interface.

This section focuses on the basic blocks of PIPE 3.0-based Gen3 PCS architecture. The PIPE 3.0-based Gen3 PCS uses a 128b/130b block encoding/decoding scheme, which is different from the 8B/10B scheme used in Gen1 and Gen2 present in the Standard PCS. The 130-bit block contains a 2-bit sync header and a 128-bit data payload. For this reason, Intel® Stratix® 10 devices include a separate Gen3 PCS that supports functionality at Gen3 speeds. This PIPE interface supports the seamless switching of Data and Clock between the Gen1, Gen2, and Gen3 data rates, and provides support for PIPE 3.0 features. The PCIe Gen3 PCS supports the PIPE interface with the Hard IP enabled, as well as with the Hard IP bypassed.

For more information about the blocks used for Gen1 and Gen2 data rates, see the Transmitter Datapath and Receiver Datapath sections of the Standard PCS Architecture chapter.

Figure 224. Gen3 PCS Block Diagram

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