L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

5.2.2.10.1. Phase Compensation Mode

The RX Core FIFO compensates for the phase difference between the read clock and write clocks. PCS_clkout_x2(rx)(RX parallel clock) clocks the write side of the RX Core FIFO and rx_coreclkin (FPGA fabric clock or rx_clkout) clocks the read side of the RX Core FIFO. Depth of RX Core FIFO is constant in this mode, therefore RX FIFO flag status can be ignored. You can tie rx_enh_data_valid with one.

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