L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.2.5. Core Clock as an Input Reference Clock

The core clock can be used as an input reference clock for fPLL only.

The core clock network routes the clock directly to the PLL. For best performance, use the dedicated reference clock pins or the reference clock network.

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