L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.5. FPGA Fabric-Transceiver Interface Clocking

The FPGA fabric-transceiver interface consists of clock signals from the FPGA fabric into the transceiver and clock signals from the transceiver into the FPGA fabric.

The transmitter channel forwards a parallel output clock tx_clkout to the FPGA fabric to clock the transmitter data and control signals into the transmitter. The receiver channel forwards a parallel output clock rx_clkout to the FPGA fabric to clock the data and status signals from the receiver into the FPGA fabric. Based on the receiver channel configuration, the parallel output clock is recovered from either the receiver serial data or the rx_clkout clock (in configurations without the rate matcher) or the tx_clkout clock (in configurations with the rate matcher).

Figure 158. FPGA Fabric—Transceiver Interface Clocking (Standard PCS Example)

The Standard PCS and Enhanced PCS tx_clkout and tx_clkout2 outputs can be driven from the following sources:

  • PCS clkout (tx)
  • PCS clkout x2 (tx)
  • pma_div_clkout (tx)

The Standard PCS and Enhanced PCS rx_clkout and rx_clkout2 outputs can be driven from the following sources:

  • PCS clkout (RX)
  • PCS clkout x2 (RX)
  • pma_div_clkout (RX)

For example, if you use the Enhanced PCS Gearbox with a 66:40 ratio, then you can use tx_pma_div_clkout with a divide-by-33 ratio to clock the write side of the TX FIFO, instead of using a PLL to generate the required clock frequency, or using an external clock source.

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