L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Public
Document Table of Contents

6.6. Steps to Perform Dynamic Reconfiguration

You can dynamically reconfigure blocks in the transceiver channel or PLL through the reconfiguration interface. The following procedure shows the steps required to reconfigure the channel and PLL blocks.
  1. Check the Enable Dynamic Reconfiguration option in the Dynamic Reconfiguration tab in the Native PHY IP.
  2. Select the desired configuration file type under Configuration Files option in the Native PHY IP.
  3. Enable the desired dynamic reconfiguration features (such as multiple reconfiguration profiles, or feature blocks (such as embedded reconfiguration streamer and NPDME).
  4. If you are using:
    1. Direct reconfiguration flow—Refer to the Logical View of the L-Tile/H-Tile Transceiver Registers for feature address and valid value of write data for the feature.
    2. IP guided reconfiguration flow—Note the settings of the base configuration and generate the corresponding configuration files. Also observe the settings of the modified configuration and generate the corresponding configuration files. Find out the differences in settings between the base and modified configurations.
    3. IP guided reconfiguration flow using multiple profiles—Create and store the parameter settings between the various configurations or profiles using configuration files. Find out the differences in settings between the various configurations or profiles using configuration files.
    4. IP guided reconfiguration flow using the embedded streamer—Refer to the Logical View of the L-Tile/H-Tile Transceiver Registers of the embedded reconfiguration streamer to stream the desired profile settings.
    5. Reconfiguration flow for special cases—Refer to the lookup registers to be accessed for each special case, such as TX PLL switching, TX PLL reference clock switching, and RX CDR reference clock switching.
  5. Assert the required channel resets (if necessary). Refer to Recommendations for Dynamic Reconfiguration for details on which resets need to be asserted.
  6. If you are reconfiguring across data rates or protocol modes or enabling/disabling PRBS, place the channels in reset.
  7. If you have background calibration enabled, disable it by setting channel offset address 0x542[0] to 0x0.
    You disabled it successfully if 0x542[0] = 0x0, 0x481[2] = 0x0, or reconfig_waitrequest is low.
  8. You must perform this step only if you are reconfiguring fPLL/ATX PLL/CDR/CMU PLL. Otherwise, go to step 11. Request PreSICE to configure the fPLL/ATX PLL/CDR/CMU PLL in preparation for reconfiguration by setting the pre_reconfig bit for the fPLL/ATX PLL/CDR/CMU PLL.
    1. 1’b1: Request PreSICE to configure the fPLL/ATX PLL/CDR/CMU PLL in reconfiguration mode.
    2. 1'b0: Reconfiguration mode not requested.
  9. You must perform this step only if you are reconfiguring fPLL/ATX PLL/CDR/CMU PLL. Otherwise, go to step 11. Also make sure you have performed step 8 before performing this step. Return the internal configuration bus access to PreSICE by writing a 0x01 to address 0x000 of the fPLL/ATX PLL/CDR/CMU PLL, and wait for PreSICE to complete the operation by monitoring the pll_cal_busy or rx_cal_busy signal or reading the pll_cal_busy or rx_cal_busy signal status from the status registers.
  10. You must perform this step if you are reconfiguring the fPLL/ATX PLL/CDR/CMU PLL. Otherwise, go to step 11. Also, make sure you have performed step 9 before performing this step. Request internal configuration bus arbitration from PreSICE.
  11. Perform the necessary reconfiguration using the flow described in the following sections: Direct Reconfiguration Flow, Native PHY or PLL IP Guided Reconfiguration Flow, and Reconfiguration Flow for Special Cases.
  12. Perform all necessary reconfiguration. If reconfiguration involved datarate or protocol mode changes, you may have to reconfigure the PMA analog parameters of the channels. Refer to Changing PMA Analog Parameters for more details.
  13. If reconfiguration involved datarate or protocol mode changes, request recalibration, and wait for the calibration to complete. Calibration is complete when tx_cal_busy or rx_cal_busy or pll_cal_busy is deasserted. For more details about calibration registers and the steps to perform recalibration, refer to Calibration.
  14. If desired, enable background calibration by setting channel offset address 0x542[0] to 0x1.
    • The background calibration feature is only available for H-tile production devices starting with Intel® Quartus® Prime Design Suite 18.1 and if the data rate is >= 17.5 Gbps.
    • Refer to Background Calibration for more information.