L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.4.2.8.2. Receiver Bit Reversal

This is a function of the word alignment block available in the Standard PCS.

You can enable the RX bit reversal feature in Basic/Custom (Standard PCS), Basic/Custom w/ Rate Match (Standard PCS) and in Standard PCS low latency mode. The word aligner is available in any mode, bit slip, manual, or synchronous state machine.

To enable this feature, select the Enable RX bit reversal and Enable rx_std_bitrev_ena port options. This adds rx_std_bitrev_ena. If there is more than one channel in the design, rx_std_bitrev_ena becomes a bus in which each bit corresponds to a channel. Provided that rx_std_bitrev_ena is asserted, the RX data received by the core shows bit reversal.

You can verify this feature by monitoring rx_parallel_data.

Figure 78. RX Bit Reversal

You can implement soft logic to perform bit reversal for the Enhanced PCS.

Refer to the Word Aligner RX Bit Reversal Feature section for more information.

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