L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

7.6. Calibration Revision History

Document Version Changes
2022.06.08 Made the following change:
  • Corrected rx_cal_busy to tx_cal_busy and RX calibration to TX calibration in step 4 of Recalibrating Only a PMA Simplex TX in a Simplex RX Merged Physical Channel.
2020.03.03 Made the following change:
  • Added "for successful device configuration" to the PCIe* note in Power-up Calibration.
2019.10.25 Made the following change:
  • Added the requirement that: The FPGA's internal oscillator cannot be used for transceiver calibration. Do not select this clock source as the Configuration clock source in the Intel® Quartus® Prime settings.
2019.03.22 Made the following changes:
  • Removed the first two steps in Recalibrating Only a PMA Simplex RX in a Simplex TX Merged Physical Channel, Recalibrating Only a PMA Simplex TX in a Simplex RX Merged Physical Channel, Recalibrating the fPLL, Recalibrating the ATX PLL, and Recalibrating the CMU PLL when it is Used as a TX PLL.
  • Added the 0x481[2] = 0x0 option to confirm control of calibration to Recalibrating a Duplex Channel (Both PMA TX and PMA RX), Recalibrating the PMA RX Only in a Duplex Channel, Recalibrating the PMA TX Only in a Duplex Channel, Recalibrating a PMA Simplex RX without a Simplex TX Merged into the Same Physical Channel, Recalibrating a PMA Simplex TX without a Simplex RX Merged into the Same Physical Channel, and Recalibrating the CMU PLL When it is Used as a TX PLL.
2018.10.05 Made the following changes:
  • Added Background Calibration.
  • In User Recalibration sections, added instructions for turning background calibration on and off.
  • Added a note to the Power-up Calibration section.
  • Updated the note in Avalon® Memory-Mapped Interface Arbitration Registers.
  • Added a note to the Capability Registers section.
  • Added a note to the Calibration section.
  • Added the "CMU PLL Capability Registers for Calibration Status" table.
  • Updated the steps in the "Recalibrating the CMU PLL when it is Used as a TX PLL" section.
2018.07.06 Made the following changes:
  • Deleted bit [1] from the Avalon® Memory-Mapped Interface Arbitration Registers.
  • Updated the instructions to return the internal configuration bus to PreSICE in Reconfiguration Interface and Arbitration with PreSICE (Precision Signal Integrity Calibration Engine).
  • Changed the calibration clock the PLL provides from a 200 to a 250-MHz in Calibration.
  • Added PMA TX calibration to Recalibrating the CMU PLL when it is Used as a TX PLL.
  • Added clarification: Each transceiver tile has a PreSICE engine. If you are using more than 24 transceiver channels in your design, the transceiver calibrates on a per tile basis. This means that channel 0 in tile 1 and channel 0 in tile 2 are calibrated concurrently, etc.
  • Added a footnote to the "PMA Capability Registers for Calibration Status" and "Transceiver Channel PMA Calibration Enable Registers" tables: CDR and CMU PLL calibration are part of RX PMA calibration.
  • Changed "Device initialization clock source" to "Configuration clock source" in Calibration and the "Calibration Clock Options" figure.
  • Make it even more obvious that the clocks must be present and at the correct frequency.
  • Removed duplicate paragraphs in User Recalibration.
  • Deleted the "Power-up Calibration Sequence for Non-PCIe Hard IP (HIP) Channels" figure.
  • Changed the offset address for returning the internal configuration bus to PreSICE.
2017.02.17 Made the following changes:
  • Updated the value of the capability register from 0x281 to 0x481 and 0x280 to 0x480 respectively.
  • Updated the Power-up Calibration sequence for non-PCIe and PCIe HIP channels.
  • Updated the use conditions to recalibrate the transceivers or the PLLs.
2016.12.21 Initial release

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