L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

7.2. Calibration Registers

The Intel® Stratix® 10 transceiver PMA and PLLs include the following types of registers for calibration:

  • Avalon® memory-mapped interface arbitration registers—enables you to request internal configuration bus access
  • Calibration enable registers—provide a convenient way to recalibrate the PMA or PLL
  • Capability registers—provide calibration and arbitration status updates through the Avalon® memory-mapped interface reconfiguration

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