L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

1.4. Overview Revision History

Document Version Changes
2021.09.09
  • Added the number of channels for Intel® Stratix® 10 GX 10M devices in the PCIe Hard IP Channel Configurations Per Transceiver Tile table.
  • Added diagram: PCIe Hard IP Channel Configurations Per Transceiver Tile (for Intel® Stratix® 10 GX 10M Devices)
  • Added table: PCIe Hard IP Channel Mapping Across all Tiles (for Intel® Stratix® 10 GX 10M Devices)
2021.03.29
  • Removed H-tile information for Intel® Agilex™ devices in the Overview section.
  • Removed the footnote to PCIe* —Gen3 x16 for H-tile in the Transceiver Tile Variants—Comparison of Transceiver Capabilities table.
  • Removed the H-Tile in Intel® Agilex™ Devices section.
2020.10.22 Made the following change:
  • Clarified that H-tiles in Intel® Agilex™ devices do not support speed grade -1 and thus have a maximum GXT transceiver data rate of 26.6 Gbps.
2020.10.05 Made the following changes:
  • Added the " Intel® Stratix® 10 GX 10M Device with 4 H-Tiles (48 Transceiver Channels)" figure.
  • Added the Intel® Stratix® 10 GX 10M Device to the "L-Tile/H-Tile Counts in Intel® Stratix® 10 GX/SX Devices (HF35, NF43, UF50, HF55, NF74)" table.
  • Added H-Tile in Intel® Agilex™ Devices.
  • Removed the H-tile hard IP 50G variant.
2020.03.03 Made the following changes:
  • Updated the Intel® Stratix® 10 TX devices in the " Intel® Stratix® 10 TX Device with 1 E-Tile and 1 H-Tile (48 Transceiver Channels)" figure and the "H- and E-Tile Counts in Intel® Stratix® 10 TX Devices (HF35, NF43, SF50, UF50, YF55)" table.
  • For GX Standard PCS data rates in GX Channel, added 12 Gbps and the note, "The 12 Gbps data rate at the receiver is only supported when the RX word aligner mode parameter is set to Manual.
2019.03.22 Made the following change:
  • Changed the data rate for E-tile Non-Return to Zero (NRZ) to 28.9 Gbps.
  • Changed 60 GXE channels/device for PAM-4 to 57.8 Gbps.
  • Updated plan of record devices.
  • Updated device configuration drawings.
2018.07.06 Made the following changes:
  • Changed the GXT data rate limit for L-Tile to 26.6 Gbps in the "Channel Types" table.
  • Changed the data rate limit for -2 speed grades on both L-Tile and H-Tile to 26.6 Gbps in the "PCS Types Supported by GXT Type Transceiver Channels" table.
  • Clarified the number of reference clocks pins in the "Reference Clock Network" figure.
  • Changed the standard PCS data rates for L-Tile and H-Tile devices in the "PCS Types Supported by GX Transceiver Channels" table.
  • Changed the backplane data rate for L-Tile GX channels in the "Channel Types" table.
2018.03.16 Made the following changes:
  • Added the operational modes description for channels in the "Transceiver Bank Architecture" section.
  • Added PCS Direct to the "GX Transceiver Channel in TX/RX Duplex Mode" figure.
  • Added a cross-reference to the "General and Datapath Parameters" table in the "GX Channel" section.
  • Added PCS Direct to the "PCS Types Supported by GX Type Transceiver Channels" table.
  • Changed the description in the "GXT Channel" section.
  • Added PCS Direct to the "GXT Transceiver Channel in TX/RX Duplex Mode" figure.
  • Updated ATX PLL description stating "An ATX PLL supports both integer frequency synthesis and coarse resolution fractional frequency synthesis (when configured as a cascade source)".
  • Removed the NF48 package from the "L-Tile/H-Tile Counts in Intel® Stratix® 10 GX/SX Devices (HF35, NF43, UF50, HF55)" table.
2017.08.11 Made the following changes:
  • Added the "Transceiver Tile Variants—Comparison of Transceiver Capabilities" table.
  • Removed the "H-Tile Transceivers" section.
  • Added description to the "L-Tile/H-Tile Layout in Stratix 10 Device Variants" section.
  • Added the "Stratix 10 Tile Layout" figure.
  • Changed the package and tile counts in the "H- and E-Tile Counts in Intel® Stratix® 10 MX Devices (NF43, UF53, UF55)" table.
  • Added separate datarate support for L-Tile and H-Tile in the "PCS Types Supported by GX Type Transceiver Channels" table.
2017.06.06 Made the following changes:
  • Removed CEI 56G support from the "Stratix 10 Transceiver Protocols, Features, and IP Core Support" table.
  • Added tile names based on the thermal models to the figures in the "Stratix 10 GX/SX H-Tile Configurations" section.
  • Added tile names based on the thermal models to the figures in the "Stratix 10 TX H-Tile and E-Tile Configurations" section.
  • Added tile names based on the thermal models to the figures in the "Stratix 10 MX H-Tile and E-Tile Configurations" section.
  • Changed the number of GXT channels that the ATX PLL can support as a transmit PLL in the "GXT Channel Usage" section.
  • Changed the number of GXT channels an ATX PLL can support in the "GXT Channel Usage" section.
  • Removed a note in the "Input Reference Clock Sources" section.
2017.03.08 Made the following changes:
  • Changed all the notes in the "GXT Channel Usage" section.
  • Changed all the notes in the "PLL Direct Connect Clock Network" section.
2017.02.17 Made the following changes:
  • Completely updated the "GXT Channel Usage" section.
2016.12.21 Initial release.

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