L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.4.4.4.3. How to Enable ODI

This procedure enables ODI through the Avalon® memory-mapped interface, allowing you to view the eye.
  1. If the device is H-tile production and background calibration is enabled, disable the background calibration:
    1. Set 0x542[0] to 0x0.
    2. Read 0x481[2] until it becomes 0x0.
  2. If the RX adaptation mode is set to manual23, set 0x148[0] to 0x1 to release adaptation from reset. Otherwise, skip this step.
  3. Set 0x169[6] to 0x1 to enable the counter to detect error bits.
  4. Set 0x168[0] to 0x1 to enable the serial bit checker for ODI.
  5. If the DFE is enabled 24:
    1. Set 0x169[2] to 0x1 to enable DFE speculation.
    2. Set 0x149[5:0] to 0x07 to read the DFE tap signs.
    3. Read 0x17F[6] 25, and store it as DFE_tap1_sign.
  6. If the DFE is disabled24:
    1. Set 0x169[2] to 0x0 to disable DFE speculation.
  7. Trade off between the ODI runtime and BER resolution by setting the number of bits to count before stopping at each horizontal or vertical point combination. Set {0x169[1:0], 0x168[5]} to:
    1. Count up to 216: 0x0.
    2. Count up to 106: 0x1.
    3. Count up to 107: 0x2.
    4. Count up to 108: 0x3.
    5. Count up to 3 x 108: 0x4.
    6. Count up to 109: 0x5.
    7. Count up to 232: 0x6.
  8. Set 0x158[5] to 0x1 to enable serial bit checker control.
  9. Set 0x12D[4] to 0x0 to disable the path from the DFE to the Avalon® memory-mapped interface testmux.
  10. If the device is H-tile production, configure the ODI bandwidth for the desired data rate by setting register {0x145[7], 0x144[7]} to the corresponding value from the following table .
    Table 94.  ODI Bandwidth Data Rate Settings for H-Tile Production
    Data Rate Register Setting
    > 25 Gbps 0x0
    25 Gbps ≥ data rate > 16 Gbps 0x2
    16 Gbps ≥ data rate > 10 Gbps 0x1
    Data rate ≤ 10 Gbps 0x3
  11. If the device is not H-tile production, configure the ODI bandwidth for the desired data rate by setting register {0x145[7], 0x144[7]} to the corresponding value from the following table .
    Table 95.  ODI Bandwidth Data Rate Settings for Non-H-Tile Production Tiles
    Data Rate Register Setting
    > 20 Gbps 0x0
    20 Gbps ≥ data rate > 12.5 Gbps 0x2
    12.5 Gbps ≥ data rate > 6.5 Gbps 0x1
    Data rate ≤ 6.5 Gbps 0x3
  12. Set 0x144[6:4] to 0x0 to set the ODI phase interpolator to 128.
  13. Set 0x140[5:3] to 0x0 to disable the ODI test pattern generator.
  14. Set 0x13C[0] to 0x0, then set it to 0x1 to reset then release the reset on the serial bit checker control logic.
  15. Set 0x171[4:1] to 0xB, to configure the Avalon® memory-mapped interface testmux to read the ODI counter values.
To save time, you can sweep the horizontal eye opening across 128 phase steps with the vertical phase set to zero. This helps determine the extent of the eye opening. Then, you can perform a refined horizontal or vertical eye sweep to capture the two-dimensional eye diagram.
23 To determine RX adaptation mode, read 0x161[5]. RX adaptation is in manual mode when 0x161[5] = 1.
24 To determine DFE mode, read 0x161[6]. DFE is disabled when 0x161[6] = 1.
25 Wait 25 µs between setting register 0x149[5:0] and reading 0x17E or 0x17F.

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