Visible to Intel only — GUID: xpl1484328042828
Ixiasoft
Visible to Intel only — GUID: xpl1484328042828
Ixiasoft
2.5.1.5. Native PHY IP Core Parameter Settings for PIPE
This section contains the recommended parameter values for this protocol. Refer to Using the Stratix® 10 L-Tile/H-Tile Transceiver Native PHY IP Core for the full range of parameter values.
Parameter | Gen1 PIPE | Gen2 PIPE | Gen3 PIPE |
---|---|---|---|
Message level for rule violations | Error | Error | Error |
VCCR_GXB and VCCT_GXB supply voltage for the Transceiver | 1_1V, 1_0V 31 | 1_1V, 1_0V 31 | 1_1V, 1_0V 31 |
Transceiver Link Type | sr, lr | sr, lr | sr, lr |
Transceiver channel type | GX | GX | GX |
Transceiver configuration rules | Gen 1 PIPE | Gen 2 PIPE | Gen 3 PIPE |
PMA configuration rules | basic | basic | basic |
Transceiver mode | TX / RX Duplex | TX / RX Duplex | TX / RX Duplex |
Number of data channels | x1: 1 x2: 2 x4: 4 x8: 8 x16: 16 |
x1: 1 x2: 2 x4: 4 x8: 8 x16: 16 |
x1: 1 x2: 2 x4: 4 x8: 8 x16: 16 |
Data rate | 2.5 Gbps | 5 Gbps | 5 Gbps 32 |
Enable datapath and interface reconfiguration | Disable | Disable | Disable |
Enable simplified data interface | Optional 33 | Optional 33 | Optional 33 |
Enable double rate transfer mode | Off | Off | Off |
Parameter | Gen1 PIPE | Gen2 PIPE | Gen3 PIPE |
---|---|---|---|
TX channel bonding mode | x1 - Not bonded x2, x4, x8, x16 - PMA & PCS Bonding |
x1 - Not bonded x2, x4, x8, x16 - PMA & PCS Bonding |
x1 - Not bonded x2, x4, x8, x16 - PMA & PCS Bonding |
PCS TX channel bonding master | Auto 34 | Auto 34 | Auto 34 |
Actual PCS TX channel bonding master | x2: 1 35 x4: 2 35 x8: 4 35 x16: 8 35 |
x2: 1 35 x4: 2 35 x8: 4 35 x16: 8 35 |
x2: 1 35 x4: 2 35 x8: 4 35 x16: 8 35 |
PCS reset sequence | Simultaneous |
Simultaneous |
Simultaneous |
TX local clock division factor | 1 | 1 | 1 |
Number of TX PLL clock inputs per channel | 1 | 1 | 2 |
Initial TX PLL clock input selection | 0 | 0 | 0 |
Enable tx_pma_iqtxrx_clkout port | On Off |
On Off |
On Off |
Enable tx_pma_elecidleport | Off | Off | Off |
Parameter | Gen1 PIPE | Gen2 PIPE | Gen3 PIPE |
---|---|---|---|
Number of CDR reference clocks | 1 | 1 | 1 |
Selected CDR reference clock | 0 | 0 | 0 |
Selected CDR reference clock frequency | 100 MHz |
100 MHz |
100 MHz |
PPM detector threshold | 1000 | 1000 | 1000 |
Enable rx_pma_iqtxrx_clkout port | Off |
Off |
Off |
Enable rx_pma_clkslip port | Off |
Off |
Off |
Enable rx_is_lockedtodata port | On Off |
On Off |
On Off |
Enable rx_is_lockedtoref port | On Off |
On Off |
On Off |
Enable rx_set_locktodata and rx_set_locktoref ports | On Off |
On Off |
On Off |
Enable PRBS verifier control and status ports | Off |
Off |
Off |
Enable rx_seriallpbken port | Off |
Off |
Off |
Parameter | Gen1 PIPE | Gen2 PIPE | Gen3 PIPE |
---|---|---|---|
Standard PCS / PMA interface width | 10 | 10 | 10 36 |
FPGA fabric / Standard TX PCS interface width | 8, 16 | 16 | 32 |
FPGA fabric / Standard RX PCS interface width | 8, 16 | 16 | 32 |
Enable 'Standard PCS' low latency Mode | Off |
Off |
Off |
TX byte serializer mode | Disabled (if FPGA fabric/standard TX/RX PCS interface width =8), Serialize x2 (if FPGA fabric/standard TX/RX PCS interface width =16) |
Serialize x2 |
Serialize x4 |
RX byte deserializer mode | Disabled (if FPGA fabric/standard TX/RX PCS interface width =8), Deserialize x2 (if FPGA fabric/standard TX/RX PCS interface width =16) |
Deserialize x2 | Deserialize x4 |
Enable TX 8B/10B encoder | On |
On |
On |
Enable TX 8B/10B disparity control | On |
On |
On |
Enable RX 8B/10B decoder | On |
On |
On |
RX rate match FIFO mode | PIPE PIPE 0ppm |
PIPE PIPE 0ppm |
PIPE PIPE 0ppm |
RX rate match insert/delete -ve pattern (hex) | 0x0002f17c (K28.5/ K28.0/) | 0x0002f17c (K28.5/ K28.0/) | 0x0002f17c (K28.5/ K28.0/) |
RX rate match insert/delete +ve pattern (hex) | 0x000d0e83 (K28.5/ K28.0/) | 0x000d0e83 (K28.5/ K28.0/) | 0x000d0e83 (K28.5/ K28.0/) |
Enable rx_std_rmfifo_full port | Off |
Off |
Off |
Enable rx_std_rmfifo_empty port | Off |
Off |
Off |
PCI Express Gen3 rate match FIFO mode | Bypass |
Bypass |
600 ppm |
Enable TX bitslip | Off |
Off |
Off |
Enable tx_std_bitslipboundarysel port | Off |
Off |
Off |
RX word aligner mode | synchronous state machine |
synchronous state machine |
synchronous state machine |
RX word aligner pattern length | 10 |
10 |
10 |
RX word aligner pattern (hex) | 0x0000 00000000017c (/K28.5/) | 0x0000 00000000017c (/K28.5/) | 0x0000 00000000017c (/K28.5/) |
Number of word alignment patterns to achieve sync | 3 | 3 | 3 |
Number of word alignment patterns to lose sync | 16 | 16 | 16 |
Number of valid data words to decrement error count | 15 | 15 | 15 |
Enable fast sync status reporting for deterministic latency SM | Off |
Off |
Off |
Enable rx_std_wa_patternalign port | Off |
Off |
Off |
Enable rx_std_wa_a1a2size port | Off |
Off |
Off |
Enable rx_std_bitslipboundarysel port | Off |
Off |
Off |
Enable rx_bitslip port | Off |
Off |
Off |
Enable TX bit reversal | Off |
Off |
Off |
Enable TX byte reversal | Off |
Off |
Off |
Enable TX polarity inversion | Off |
Off |
Off |
Enable tx_polinv port | Off |
Off |
Off |
Enable RX bit reversal | Off |
Off |
Off |
Enable rx_std_bitrev_ena port | Off |
Off |
Off |
Enable RX byte reversal | Off |
Off |
Off |
Enable rx_std_byterev_ena port | Off |
Off |
Off |
Enable RX polarity inversion | Off |
Off |
Off |
Enable rx_polinv port | Off |
Off |
Off |
Enable rx_std_signaldetect port | Off |
Off |
Off |
Enable PCIe dynamic datarate switch ports | Off |
On |
On |
Enable PCIe electrical idle control and status ports | On |
On |
On |
Enable PCIe pipe_hclk_in and pipe_hclk_out ports | On |
On |
On |
Parameter | Gen1 PIPE | Gen2 PIPE | Gen3 PIPE |
---|---|---|---|
Enable PCS reset status ports | Off | Off | Off |
TX Core Interface FIFO mode | Phase compensation | Phase compensation | Phase compensation |
TX FIFO partially full threshold | 5 | 5 | 10 |
TX FIFO partially empty threshold | 2 | 2 | 2 |
Enable tx_fifo_full port | Off | Off | Off |
Enable tx_fifo_empty port | Off | Off | Off |
Enable tx_fifo_pfull port | Off | Off | Off |
Enable tx_fifo_pempty port | Off | Off | Off |
Enable tx_dll_lock port | Off | Off | Off |
RX Core Interface FIFO mode (PCS FIFO - Core FIFO) | Phase compensation | Phase compensation | Phase compensation |
RX FIFO partially full threshold | 5 | 5 | 10 |
RX FIFO partially empty threshold | 2 | 2 | 2 |
Enable RX FIFO alignment word deletion (Interlaken) | Off | Off | Off |
Enable RX FIFO control word deletion (Interlaken) | Off | Off | Off |
Enable rx_data_valid port | Off | Off | Off |
Enable rx_fifo_full port | Off | Off | Off |
Enable rx_fifo_empty port | Off | Off | Off |
Enable rx_fifo_pfull port | Off | Off | Off |
Enable rx_fifo_pempty port | Off | Off | Off |
Enable rx_fifo_del port (10GBASE-R) | Off | Off | Off |
Enable rx_fifo_insert port (10GBASE-R) | Off | Off | Off |
Enable rx_fifo_rd_en port | Off | Off | Off |
Enable rx_fifo_align_clr port (Interlaken) | Off | Off | Off |
Selected tx_clkout clock source | PCS clkout | PCS clkout | PCS clkout |
Enable tx_clkout2 port | On | On | On |
Selected tx_clkout2 clock source | PCS clkout x2 | PCS clkout x2 | PCS clkout x2 |
TX pma_div_clkout division factor | Disabled | Disabled | Disabled |
Selected tx_coreclkin clock network | Dedicated Clock | Dedicated Clock | Dedicated Clock |
Selected TX PCS bonding clock network | Dedicated Clock | Dedicated Clock | Dedicated Clock |
Enable tx_coreclkin2 port | Off | Off | Off |
Selected rx_clkout clock source | PCS clkout | PCS clkout | PCS clkout |
Enable rx_clkout2 port | Off | Off | Off |
Selected rx_clkout2 clock source | Off | Off | Off |
RX pma_div_clkout division factor | Disabled | Disabled | Disabled |
Selected rx_coreclkin clock network | Dedicated Clock | Dedicated Clock | Dedicated Clock |
Latency Measurement Options | Off | Off | Off |
Enable latency measurement ports | Off | Off | Off |
Parameter | Gen1 PIPE | Gen2 PIPE | Gen3 PIPE |
---|---|---|---|
TX PMA analog mode rules | pcie_cable | pcie_cable | pcie_cable |
Use default TX PMA analog settings | On / Off (Use the values listed below if this option is disabled) | On / Off (Use the values listed below if this option is disabled) | On / Off (Use the values listed below if this option is disabled) |
Output swing level (VOD) | 24 | 24 | 31 |
Pre-emphasis First pre-tap polarity | Negative | Negative | Negative |
Pre-emphasis first pre-tap magnitude | 0 | 0 | 0 |
Pre-emphasis First post-tap polarity | Negative | Negative | Negative |
Pre-emphasis first post tap magnitude | 8 | 8 | 0 |
Slew rate control | 4 | 5 | 5 |
On-chip termination | R_r1 | R_r1 | R_r1 |
High speed compensation | Disable | Disable | Enable |
RX PMA analog mode rules | User_custom | User_custom | User_custom |
Use default RX PMA analog settings | On / Off (Use the values listed below if this option is Off) | On / Off (Use the values listed below if this option is Off) | On / Off (Use the values listed below if this option is Off) |
RX Adaptation mode | Manual CTLE, Manual VGA, DFE Off |
Manual CTLE,
|