L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Document Table of Contents

2.5.1. PCI Express (PIPE)

You can use Intel® Stratix® 10 transceivers to implement a complete PCI Express solution for Gen1, Gen2, and Gen3, at datarates of 2.5, 5.0, and 8 Gbps, respectively.

To implement PCI Express, you must select the external oscillator as the data path configuration clock. This allows you to set the frequency accurately through OSC_CLK_1. You must provide a free running and stable clock to the OSC_CLK_1 pin for transceiver calibration. Refer to Calibration for more details.

Configure the transceivers for PCIe functionality using one of the following methods:

  • Intel® Stratix® 10 Hard IP for PCIe

    This is a complete PCIe solution that includes the Transaction, Data Link, and PHY/MAC layers. The Hard IP solution contains dedicated hard logic, which connects to the transceiver PHY interface.

  • PIPE Gen1/Gen2/Gen3 Transceiver Configuration Rules for the Native PHY IP Core

    Use the Native PHY IP core to configure the transceivers in PCIe mode, giving access to the PIPE interface (commonly called PIPE mode in transceivers). This mode enables you to connect the transceiver to a third-party MAC to create a complete PCIe solution.

    The PIPE specification (version 3.0) provides implementation details for a PCIe-compliant physical layer. The Native PHY IP Core for PIPE Gen1, Gen2, and Gen3 supports x1, x2, x4, x8 or x16 operation for a total aggregate bandwidth ranging from 2.5 to 128 Gbps. The x1 configuration uses the x1 clock network and the channel is non-bonded. The x2, x4, x8 and x16 configurations support channel bonding for two-lane, four-lane, eight-lane, and sixteen-lane links. In these bonded channel configurations, the PCS and PMA blocks of all bonded channels share common clock and reset signals.

Gen1 and Gen2 modes use 8B/10B encoding, which has a 20% overhead to overall link bandwidth. Gen3 modes use 128b/130b encoding, which has an overhead of less than 2%. Gen1 and Gen2 modes use the Standard PCS, and Gen3 mode uses the Gen3 PCS for its operation.

Table 97.   Intel® Stratix® 10 PCIe Hard IP and PIPE Support Configuration
Support Intel® Stratix® 10 Hard IP for PCI Express L-Tile/H-Tile Native PHY IP Core for PCI Express (PIPE)
Gen1, Gen2, and Gen3 datarates Yes Yes
MAC, data link, and transaction layer Yes User implementation in FPGA fabric
Transceiver interface Hard IP through PIPE 3.0 based interface
  • PIPE 2.0 for Gen1 and Gen2
  • PIPE 3.0 based for Gen3 with Gen1/Gen2 support