220.127.116.11.3. KR-FEC Functionality for 64B/66B Based Protocols
For example, you can implement the Superlite II V2 protocol running four bonded lanes at 16 Gbps across a lossy backplane (close to 30 dB of IL at 8 GHz), and use the KR-FEC block in addition to RX equalization, to further reduce BER. Note that you incur additional latency that inherently occurs when using FEC. For the KR-FEC implementation mentioned in the example above, the latency is approximately an additional 40 parallel clock cycles for the full TX and RX path). The latency numbers depend on the actual line rate and other PCS blocks used for the protocol implementation. Refer to the Intel FPGA Wiki for more information about high speed transceiver demo designs.
Refer to the KR FEC Blocks and RX KR FEC Blocks sections for more information about the KR-FEC blocks.
Refer to the 64B/66B Encoder and Transmitter State Machine (TX SM) and 64B/66B Decoder and Receiver State Machine (RX SM) sections for more information about the 64B/66B encoder and decoder.