L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

A.1.1. ATX PLL Calibration

ATX PLL Calibration allows users to optimize the ATX PLL performance when changing data rates.
Name Address Type Attribute Name Encodings
Internal configuration bus arbitration register for ATX PLL

0x000[0]

read-write pcs_arbiter_ctrl

This bit arbitrates the control of internal configuration bus

Write 1'b0 to control the internal configuration bus.

Write 1'b1 to pass the internal configuration bus control to PreSICE.

ATX PLL Calibration Status

0x000[1]

read-write pcs_cal_done

Status for calibration done or not done

This is the inverted cal_busy signal.

1'b1: calibration done

1'b0: calibration not done

ATX PLL calibration enable

0x100[0]

read-write lc_calibration

ATX PLL calibration enable

1'b1: ATX PLL calibration enable on

1'b0: ATX PLL calibration enable off

Request PreSICE to configure the ATX PLL in preparation for reconfiguration

0x100[1]

read-write pre_reconfig

Request PreSICE to configure the ATX PLL in preparation for reconfiguration:

1'b1: Request PreSICE to configure the PLL in reconfiguration mode

1'b0: Reconfiguration mode not requested

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