V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents XCVR_RX_BYPASS_EQ_STAGES_234

Pin Planner and Assignment Editor Name

Receiver Equalizer Stage 2, 3, 4 Bypass


Bypass continuous time equalizer stages 2, 3, and 4 to save power. This setting eliminates significant AC gain on the equalizer and is appropriate for chip-to-chip short range communication on a PCB. Assigning a value to this setting and XCVR_ANALOG_SETTINGS_PROTOCOL results in a Intel® Quartus® Prime Fitter error as shown in the following example:

Error resolving parameter "pm_rx_sd_bypass_eqz_stages_234" value
on instance "pci_interface_ddf2:u_pci_interface_2|
sv_rx_pma_inst|rx_pmas[8].rx_pma.rx_pma_buf": Only one QSF
setting for the parameter is allowed.


  • All_Stages_Enabled
  • Bypass_Stages

Assign To

Pin - RX serial data

Note: This setting can be used for data rates upto 5 Gbps for backplane applications, and 8 Gbps for chip-to-chip applications.

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