ID 683171
Date 7/26/2022
Public

## 15.5.3. 10G PCS Interface

The following figure illustrates the top-level signals of the 10G PCS. If you enable both the 10G PCS and Standard PCS your top‑level HDL file includes all the interfaces for both.

Figure 83. Arria V Native PHY 10G PCS Interfaces

The following table describes the signals available for the 10G PCS datapath. When you enable both the 10G and Standard datapaths, both sets of signals are included in the top‑level HDL file for the Native PHY.

Note: In the following table, the column labeled “Synchronous to tx_10_coreclkin/rx_10g_coreclkin” refers to cases where the phase compensation FIFO is not in register mode.
Table 293.  Name Dir Synchronous to tx_10g_coreclkin/rx_10g_coreclkin Description
Name Dir Synchronous to tx_10g_coreclkin/rx_10g_coreclkin Description
Clocks
tx_10g_coreclkin
[<n>-1:0]


Input

TX parallel clock input that drive the write side of the TX FIFO.

rx_10g_coreclkin
[<n>-1:0]


Input

RX parallel clock input that drives the read side of the RX FIFO.

tx_10g_clkout
[<n>-1:0]


Output

TX parallel clock output for the TX PCS.

rx_10g_clkout
[<n>-1:0]


Output

RX parallel clock output which is recovered from the RX data stream.

rx_10g_clk33out
[<n>-1:0]


Output

This clock is driven by the RX deserializer. Its frequency is RX CDR PLL clock frequency divided by 33 or equivalently the RX PMA data rate divided by 66. It is typically used for ethernet applications that use 66b/64b decoding.

TX FIFO
tx_10g_control
[9<n>-1:0]


Input

Yes

TX control signals for the Interlaken, 10GBASE‑R, and Basic protocols. Synchronous to tx_10g_coreclk_in. The following signals are defined:

Interlaken mode:

• [8]: Active-high synchronous error insertion control bit
• [7:3]: Not Used
tx_10g_control
[9<n>-1:0] (continued)


Input

Yes

• [2]: Inversion signal, must always be set to 1'b0.
• [1]: Sync Header, 1 indicates a control word
• [0]: Sync Header, 1 indicates a data word

10G BaseR mode:

• [8]: Active-high synchronous error insertion control signal
• [7]: MII control signal for tx_data[63:56]
• [6]: MII control signal for tx_data[55:48]
• [5]: MII control signal for tx_data[47:40]
• [4]: MII control signal for tx_data[39:32]
• [3]: MII control signal for tx_data[31:24]
• [2]: MII control signal for tx_data[23:16]
• [1]: MII control signal for tx_data[15:8]
• [0]: MII control signal for tx_data[7:0]

Basic mode: 67-bit word width:

• [8:3]: Not used
• [2]: Inversion Bit - must always be set to 1'b0.
• [1]: Sync Header, 1 indicates a control word)
• [0]: Sync Header, 1 indicates a data word)

Basic mode: 66-bit word width:

• [8:2]: Not used
• [1]: Sync Header, 1 indicates a control word)
• [0]: Sync Header, 1 indicates 1 data word)

Basic mode: 64-bit, 50-bit, 40-bit, 32-bit word widths:

[8:0]: Not used

tx_10g_data_valid
[<n>-1:0]


Input

Yes

When asserted, indicates if tx_data is valid Use of this signal depends upon the protocol you are implementing, as follows:

• 10G BASE‑R: Tie to 1'b1
• Interlaken: Acts as control for FIFO write enable. You should tie this signal to tx_10g_fifo_pempty.
• Basic with phase compensation FIFO: Tie to 1'b1 as long as tx_coreclkin = data_rate/pld_pcs interface width. Otherwise, tie this signal to tx_10g_fifo_pempty.
• Basic with phase compensation FIFO in register mode. This mode only allows a 1:1 gear box ratio such as 32:32 and 64:64; consequently, you can tie tx_10g_data_valid to 1’b1.
tx_10g_fifo_full
[<n>-1:0]


Output

Yes

When asserted, indicates that the TX FIFO is full. Synchronous to tx_std_clkout,

tx_10g_fifo_pfull
[<n>-1:0]


Output

Yes

When asserted, indicates that the TX FIFO is partially full.

tx_10g_fifo_empty
[<n>-1:0]


Output

No

TX FIFO empty flag. Synchronous to tx_std_clkout. This signal is pulse‑stretched; you must use a synchronizer.

tx_10g_fifo_pempty
[<n>-1:0]


Output

No

TX FIFO partially empty flag. Synchronous to tx_std_clkout. This signal is pulse‑stretched; you must use a synchronizer.

tx_10g_fifo_del
[<n>-1:0]


Output

Yes

When asserted, indicates that a word has been deleted from the rate match FIFO. This signal is used for the 10GBASE‑R protocol.

tx_10g_fifo_insert
[<n>-1:0]


Output

No

When asserted, indicates that a word has been inserted into the rate match FIFO. This signal is used for the 10GBASE‑R protocol. This signal is pulse‑stretched, you must use a synchronizer.

RX FIFO
rx_10g_control
[10<n>-1:0]


Output

Yes

RX control signals for the Interlaken, 10GBASE-R, and Basic protocols. The following signals are defined:

Interlaken mode:

• [9]: Active‑high synchronous status signal that indicates when block lock and frame lock are achieved.
• [8]: Active‑high synchronous status signal that indicates a synchronization header, metaframe or CRC32 error.
• [7]: Active‑high synchronous status signal that indicates the Diagnostic Word location within a metaframe.
• [6]: Active‑high synchronous status signal that indicates the SKIP Word location within a metaframe.
• [5]: Active‑high synchronous status signal that indicates the Scrambler State Word location within a metaframe.
• [4]: Active-high synchronous status signal that indicates the Synchronization Word location within a metaframe.
• [3]: Active-high synchronous status signal that indicates the Payload Word location within a metaframe.
• [2]: Inversion signal, when asserted indicates that the polarity of the signal has been inverted.
• [1]: Synchronization header, 1 indicates control word.
• [0]: Synchronization header, 1 indicates data word.

10GBASE‑R mode:

• [9]: Active-high synchronous status signal indicating when Block Lock is achieved
• [8]: Active-high status signal that indicates a Idle/OS deletion
• [7]: MII control signal for tx_data[63:56]
• [6]: MII control signal for tx_data[55:48]
• [5]: MII control signal for tx_data[47:40]
• [4]: MII control signal for tx_data[39:32]
• [3]: MII control signal for tx_data[31:24]
• [2]: MII control signal for tx_data[23:16]
• [1]: MII control signal for tx_data[15:8]
• [0]: MII control signal for tx_data[7:0]
rx_10g_control
[10<n>-1:0] (continued)


Basic mode: 67-bit mode with Block Sync:

• [9]: Active-high synchronous status signal that indicates when Block Lock is achieved.
• [8]: Active-high synchronous status signal that indicates a sync header error
• [7:3]: Not used [2]: Used
• [1]: Synchronization header, a 1 indicates control word
• [0]: Synchronization header, a 1 indicates data word

Basic mode: 66-bit mode with Block Sync:

[9]: Active-high synchronous status signal that indicates when Block Lock is achieved.

[8]: Active-high synchronous status signal that indicates a sync header error.

[7:2]: Not used

• [1]: Synchronization header, a 1 indicates control word
• [0]: Synchronization header, a 1 indicates data word

Basic mode: 67-bit mode without Block Sync:

[9:3]: Not used

66-bit mode without Block Sync:

[9:2]: Not used

• [1]: Synchronization header, a 1 indicates control word
• [0]: Synchronization header, a 1 indicates data word

Basic mode: 64-bit, 50-bit, 40-bit and 32-bit modes:

[9:0]: Not used

rx_10g_fifo_rd_en
[<n>-1:0]


Input

Yes

Active high read enable signal for RX FIFO. Asserting this signal reads 1 word from the RX FIFO.

rx_10g_data_valid
[<n>-1:0]


Output

Yes

Active valid data signal with the following use:

• 10GBASE‑R: Always high
• Interlaken: Toggles indicating when rx_data is valid.
• Basic - Phase compensation: Toggles indicating when rx_data is valid.
• Basic - Register: Toggles indicating when rx_data is valid.
rx_10g_fifo_full
[<n>-1:0]


Output

No

Active high RX FIFO full flag. Synchronous to rx_10g_clkout. This signal is pulse-stretched; you must use a synchronizer.

rx_10g_fifo_pfull
[<n>-1:0]


Output

No

RX FIFO partially full flag. Synchronous to rx_10g_clkout. This signal is pulse-stretched; you must use a synchronizer.

rx_10g_fifo_empty
[<n>-1:0]


Output

Yes

Active high RX FIFO empty flag,

rx_10g_fifo_pempty
[<n>-1:0]


Output

Yes

Active high. RX FIFO partially empty flag,

rx_10g_fifo_align_clr
[<n>-1:0]


Input

Yes

For the Interlaken protocol, this signal clears the current word alignment when the RX FIFO acts as a deskew FIFO. When it is asserted, the RX FIFO is reset and searches for a new alignment pattern.

rx_10g_fifo_align_en
[<n>-1:0]


Input

Yes

For the Interlaken protocol, you must assert this signal to enable the RX FIFO for alignment.

rx_10g_align_val
[<n>-1:0]


Output

Yes

For the Interlaken protocol, an active high indication that the alignment pattern has been found

Rx_10g_fifo_del
[<n>-1:0]


Output

No

When asserted, indicates that a word has been deleted from the TX FIFO. This signal is used for the 10GBASE‑R protocol. This signal is pulse-stretched; you must use a synchronizer.

Rx_10g_fifo_insert
[<n>-1:0]


Output

Yes

Active-high 10G BaseR RX FIFO insertion flag

When asserted, indicates that a word has been inserted into the TX FIFO. This signal is used for the 10GBASE‑R protocol.

CRC32
rx_10g_crc32err
[<n>-1:0]


Output

No

For the Interlaken protocol, asserted to indicate that the CRC32 Checker has found a CRC32 error in the current metaframe. Is is asserted at the end of current metaframe. This signal is pulse‑stretched; you must use a synchronizer.

Frame Generator
tx_10g_diag_status
[2<n>-1:0]


Input

No

For the Interlaken protocol, provides diagnostic status information reflecting the lane status message contained in the Framing Layer Diagnostic Word (bits[33:32]). This message is inserted into the next Diagnostic Word generated by the Frame Generation Block. The message must be held static for 5 cycles before and 5 cycles after the tx_frame pulse.

tx_10g_burst_en
[<n>-1:0]


Input

No

For the Interlaken protocol, controls frame generator reads from the TX FIFO. Latched once at the beginning of each metaframe.When 0, the frame generator inserts SKIPs. When 1, the frame generator reads data from the TX FIFO. Must be held static for 5 cycles before and 5 cycles after the tx_frame pulse.

tx_10g_frame
[<n>-1:0]


Output

No

For the Interlaken protocol, asserted to indicate the beginning of a new metaframe inside the frame generator. This signal is pulse‑stretched; you must use a synchronizer.

Frame Synchronizer
rx_10g_frame
[<n>-1:0]


Output

No

For the Interlaken protocol, asserted to indicate the beginning of a new metaframe inside the frame synchronizer. This signal is pulse‑stretched, you must use a synchronizer. This signal is pulse‑stretched; you must use a synchronizer.

rx_10g_frame_lock
[<n>-1:0]


Output

No

For the Interlaken protocol, asserted to indicate that the frame synchronizer state machine has achieved frame lock. This signal is pulse‑stretched, you must use a synchronizer. This signal is pulse‑stretched; you must use a synchronizer.

Rx_10g_pyld_ins
[<n>-1:0]


Output

No

For the Interlaken protocol, asserted to indicate a SKIP Word was not received by the frame synchronizer in a SKIP Word location within the metaframe. This signal is pulse‑stretched, you must use a synchronizer. This signal is pulse‑stretched; you must use a synchronizer.

rx_10g_frame_mfrm_err
[<n>-1:0]


Output

No

For the Interlaken protocol, asserted to indicate an error has occurred in the metaframe. This signal is pulse‑stretched, you must use a synchronizer. This signal is pulse‑stretched; you must use a synchronizer.

rx_10g_frame_sync_err
[<n>-1:0]


Output

No

For the Interlaken protocol, asserted to indicate a synchronization Control Word error was received in a synchronization Control Word location within the metaframe.

This signal is sticky if block lock is lost and does not update until block lock is re‑established.This signal is pulse‑stretched; you must use a synchronizer.

rx_10g_scram_err
[<n>-1:0]


Output

No

For the Interlaken protocol, asserted to indicate, Scrambler Control Word errors in a Scrambler Control Word location within the metaframe.

This signal is sticky during the loss of block lock and does not update until block lock is re‑established. This signal is pulse‑stretched; you must use a synchronizer.

rx_10g_frame_skip_ins
[<n>-1:0]


Output

No

For the Interlaken protocol, asserted to indicate to a SKIP Word was received by the frame synchronizer in a non-SKIP Word location within the metaframe. This signal is pulse‑stretched; you must use a synchronizer.

rx_10g_frame_skip_err
[<n>-1:0]


Output

No

For the Interlaken protocol, asserted to indicate a Skip Control Word error was received in a Skip Control Word location within the metaframe.

This signal is sticky during the loss of block lock and does not update until block lock is re‑established. This signal is pulse‑stretched; you must use a synchronizer.

rx_10g_frame_diag_err[<n>-1:0]


Output

No

For the Interlaken protocol, asserted to indicate a Diagnostic Control Word error was received in a Diagnostic Control Word location within the metaframe.

This signal is sticky during the loss of block lock and does not update until block lock is re‑established. This signal is pulse‑stretched; you must use a synchronizer.

rx_10g_frame_diag_status
[2<n>-1:0]


Output

No

For the Interlaken protocol, reflects the lane status message contained in the framing layer Diagnostic Word (bits[33:32]). This information is latched when a valid Diagnostic Word is received in a Diagnostic Word Metaframe location. This signal is pulse‑stretched; you must use a synchronizer.

Block Synchronizer
rx_10g_blk_lock
[<n>-1:0]


Output

No

Active-high status signal that is asserted when block synchronizer acquires block lock. Valid for the 10GBASE‑R and Interlaken protocols, and any basic mode that uses the lock state machine to achieve and monitor block synchronization for word alignment. Once the block synchronizer acquires block lock, it takes at least 16 errors for rx_10g_blk_lock to be deasserted.

rx_10g_blk_sh_err
[<n>-1:0]


Output

No

Error status signal from block synchronizer indicating an invalid synchronization header has been received. Valid for the 10GBASE‑R and Interlaken protocols, and any legal basic mode that uses the lock state machine to achieve and monitor block synchronization for word alignment. Active only after block lock is achieved. This signal is generated by rx_pma_clk and is pulse-stretched by 3 clock cycles. You must use a synchronizer.

Bit-Slip Gearbox Feature Synchronizer
rx_10g_bitslip
[<n>-1:0]


Input

No

User control bit‑slip in the RX Gearbox. Slips one bit per rising edge pulse.

tx_10g_bitslip
[7<n>-1:0]


Input

No

TX bit‑slip is controlled by tx_bitslip port.

Shifts the number of bit location specified by tx_bitslip. The maximum shift is <pcswidth-1>.

64b/66b
rx_10g_clr_errblk_count
[<n>-1:0]


Input

No

For the 10GBASE‑R protocol, asserted to clear the error block counter which counts the number of times the RX state machine enters the RX error state.

BER
rx_10g_highber
[<n>-1:0]


Output

No

For the 10GBASE‑R protocol, status signal asserted to indicate a bit error ratio of >10–4. A count of 16 in 125us indicates a bit error ratio of >10–4. Once asserted, it remains high for at least 125 us.

rx_10g_clr_highber_cnt
[<n>-1:0]


Input

No

For the 10GBASE‑R protocol, status signal asserted to clear the BER counter which counts the number of times the BER state machine enters the BER_BAD_SH state. This signal has no effect on the operation of the BER state machine.

PRBS
rx_10g_prbs_done

Output

When asserted, indicates the verifier has aligned and captured consecutive PRBS patterns and the first pass through a polynomial is complete.

rx_10g_prbs_err

Output

When asserted, indicates an error only after the rx_10g_prbs_done signal has been asserted. This signal pulses for every error that occurs. An error can only occur once per word. This signal indicates errors for both the PRBS and pseudo-random patterns.

rx_10g_prbs_err_clr

Input

When asserted, clears the PRBS pattern and de-asserts the rx_10g_prbs_done signal.