V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

12.5.3. PLL Reconfiguration Parameters for Deterministic Latency PHY

The section describes the PLL Reconfiguration options for the Deterministic Latency PHY IP core.

This table lists the PLL Reconfiguration options. For more information about transceiver reconfiguration registers, refer to PLL Reconfiguration.
Table 168.  PLL Reconfiguration Options
Name Value Description
Allow PLL/CDR Reconfiguration On/Off You must enable this option if you plan to reconfigure the PLLs in your design. This option is also required to simulate PLL reconfiguration.
Number of TX PLLs Device dependent Specifies the number of TX PLLs that can be used to dynamically reconfigure channels to run at multiple data rates. If your design does not require transceiver TX PLL dynamic reconfiguration, set this value to 1. The number of actual physical PLLs that are implemented depends on the selected clock network. Each channel can dynamically select between n PLLs, where n is the number of PLLs specified for this parameter.
Note: For more details, refer to the Transceiver Clocking chapter in the device handbook for the device family you are using.
Number of reference clocks 1-5 Specifies the number of input reference clocks. More than one reference clock may be required if your design reconfigures channels to run at multiple frequencies.
Main TX PLL logical index 0-3 Specifies the index for the TX PLL that should be instantiated at startup. Logical index 0 corresponds to TX PLL0, and so on.
Main TX PLL input clock source 0-3 Specifies the index for the TX PLL input clock that should be instantiated at startup. Logical index 0 corresponds to input clock 0 and so on.
CDR PLL input clock source 0-4 Specifies the index for the CDR PLL input clock that should be instantiated at startup. Logical index 0 corresponds to input clock 0 and so on.
TX PLL (0–3) (Refer to General Options for a detailed explanation of these parameters.)
PLL Type CMU Specifies the PLL type.
Base data rate

1 × Lane rate

2 × Lane rate

4 × Lane rate

Specifies Base data rate.
Input clock frequency Variable Specifies the frequency of the PLL input reference clock. The PLL must generate an output frequency that equals the Base data rate/2. You can use any Input clock frequency that allows the PLLs to generate this output frequency.
Selected input clock source 0-4 Specifies the index of the input clock for this TX PLL. Logical index 0 corresponds to input clock 0 and so on.
Channel Interface
Enable channel interface On/Off Turn this option on to enable PLL and datapath dynamic reconfiguration. When you select this option, the width of tx_parallel_data and rx_parallel_data buses increases in the following way:
  • The rx_parallel_data bus is 64 bits per lane; however, only the low‑order number of bits specified by the FPGA fabric transceiver interface width contain valid data.
  • The tx_parallel_databus is 44 bits per lane; however, only the low‑order number of bits specified by the FPGA fabric transceiver interface width contain valid data for each lane.

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