V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents Reset Control Registers–Automatic Reset Controller

Table 143.  Reset Control Registers–Automatic Reset Controller
Word Addr Bits R/W Register Name Description
0x041 [31:0] RW reset_ch_bitmask Reset controller channel bit mask for reset registers at 0x042 and 0x044. The default value is all 1s. Channel <n> can be reset when bit <n> = 1.
0x042 [1:0] R reset_status (read) Reading bit 0 returns the status of the reset controller TX ready bit. Reading bit 1 returns the status of the reset controller RX ready bit.

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