V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

10.4.6.4. PMA Control and Status Registers

Table 145.  PMA Control and Status Registers
Word Addr Bits R/W Register Name Description
0x061 [31:0] RW phy _ serial _ loopback Writing a 1 to channel <n> puts channel <n> in serial loopback mode.
0x063 [31:0] R pma_rx_signaldetect When channel <n> =1, indicates that receive circuit for channel <n> senses the specified voltage exists at the RX input buffer.
0x064 [31:0] RW pma_rx_set_locktodata When set, programs the RX CDR PLL to lock to the incoming data. Bit <n> corresponds to channel <n> .
0x065 [31:0] RW pma_rx_set_locktoref When set, programs the RX CDR PLL to lock to the reference clock. Bit <n> corresponds to channel <n> .
0x066 [31:0] RO pma_rx_is_lockedtodata When 1, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to LTD mode. Bit <n> corresponds to channel <n> .
0x067 [31:0] RO pma_rx_is_lockedtoref When 1, indicates that the RX CDR PLL is locked to the reference clock. Bit <n> corresponds to channel <n> .

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