V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

11.8. Low Latency PHY Interfaces

The following figure illustrates the top-level signals of the Custom PHY IP Core. The variables in this figure represent the following parameters:

  • <n>—The number of lanes
  • <w>—The width of the FPGA fabric to transceiver interface per lane
Figure 57. Top-Level Low Latency Signals
Note: By default block diagram shown in the MegaWizard Plug-In Manager labels the external pins with the interface type and places the interface name inside the box. The interface type and name are used in the _hw.tcl file that describes the component. If you turn on Show signals, the block diagram displays all toplevel signal names.

For more information about _hw.tcl files refer to refer to the Component Interface Tcl Reference chapter in volume 1 of the Intel® Quartus® Prime Handbook.

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