V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

6.2.1. Parameter Settings

You customize the PHY IP core by specifying the parameters in the parameter editor in the Intel® Quartus® Prime software. The parameter editor enables only the parameters that are applicable to the selected speed.

Table 72.  Multi-rate Ethernet PHY IP Core Parameters







The operating speed of the PHY.
Enable IEEE 1588 Precision Time Protocol On, Off

Select this parameter for the PHY to provide latency information to the MAC. The MAC requires this information if it enables the IEEE 1588v2 feature.

This parameter is enabled only for 2.5G and 1G/2.5G.

PHY ID (32 bit) 32-bit value

An optional 32-bit unique identifier:

  • Bits 3 to 24 of the Organizationally Unique Identifier (OUI) assigned by the IEEE
  • 6-bit model number
  • 4-bit revision number

If unused, do not change the default value, which is 0x00000000.

Reference clock frequency for 10 GbE (MHz) 322.265625, 644.53125 Specify the frequency of the reference clock for 10GbE.
Selected clock network for 1GbE x1, ×N

Select the clock network for the 1GbE TX PLL. This parameter applies to Arria V devices only.

Selected clock network for 2.5GbE x1, ×N

Select the clock network for the 2.5GbE TX PLL. This parameter applies to Arria V devices only.

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