V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

9.10. PHY for PCIe (PIPE) Optional Status Interface

This section describes the signals the optional status signals.
Table 117.  Status Signals
Signal Name 6 Direction Signal Name
tx_ready Output When asserted, indicates that the TX interface has exited the reset state and is ready to transmit.
rx_ready Output When asserted, indicates that the RX interface has exited the reset state and is ready to receive.
pll_locked[<p>-1:0] Output When asserted, indicates that the TX PLL is locked to the input reference clock. This signal is asynchronous.
rx_is_lockedtodata[<n>-1:0] Output When asserted, the receiver CDR is in to lock-to-data mode. When deasserted, the receiver CDR lock mode depends on the rx_locktorefclk signal level.
rx_is_lockedtoref[<n>-1:0] Output Asserted when the receiver CDR is locked to the input reference clock. This signal is asynchronous.
rx_syncstatus[<d><n>/8-1:0] Output Indicates presence or absence of synchronization on the RX interface. Asserted when word aligner identifies the word alignment pattern or synchronization code groups in the received data stream.
rx_signaldetect[<d><n>/8-1:0] Output When asserted indicates that the lane detects a sender at the other end of the link.
6 <n> is the number of lanes. <d> is the deserialization factor. < p> is the number of PLLs.

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