V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

17.13. Transceiver Reconfiguration Controller ATX PLL Calibration Registers

The ATX PLL Calibration registers allow you to rerun ATX calibration after power up. The Transceiver Reconfiguration Controller automatically runs ATX calibration at power up.
Note: You may need to rerun ATX calibration if you reset an ATX PLL and it does not lock after the specified lock time.

The following table lists the direct access ATX registers that you can access using Avalon-MM reads and writes on reconfiguration management interface.

Note: All undefined register bits are reserved.
Table 333.   ATX Tuning Registers
ATX Addr Bits R/W Register Name Description
7’h30 [9:0] RW logical channel number The logical channel number. The Transceiver Reconfiguration Controller maps the logical address to the physical address.
7’h32 [9] R control and status

Error. When asserted, indicates an invalid channel or address. This bit is asserted after a write operation if the selected logical channel number selects a logical channel interface that is not connected to an ATX PLL. It is also be asserted if the tuning algorithm failed to converge on a working setting after a manual calibration.

[8] R Busy. When asserted, indicates that a reconfiguration operation is in progress.
[1] W Read. Writing a 1 to this bit triggers a read operation.
[0] W Write. Writing a 1 to this bit triggers a write operation.
7’h33 [3:0] RW atx_offset Specifies the 4-bit register address used for indirect accesses on the reconfiguration bus. Refer to Table 334 for offsets and values.
7’h34 [15:0] RW data Reconfiguration data for the transceiver PHY registers.
Table 334.  ATX PLL Tuning Offsets and Values
Offset Bits R/W Register Name Description
0x0 [0] RW Control Writing a 1 to this bit triggers ATX PLL calibration. This register self-clears. Unused bits of this register must be set to 0. The tx_cal_busy signal is asserted at initial runtime or if you reset the reconfiguration controller. It is not asserted if you manually re-trigger the ATX PLL calibration process. Writing a 1 to this bit will not trigger ATX PLL calibration if the PLL is already locked.
0x1 [1] RW   Writing a 1 to this bit triggers the ATX PLL calibration even if the PLL is already locked.

Refer to Changing Transceiver Settings Using Register-Based Reconfiguration for the procedures you can use to control ATX tuning.

Did you find the information on this page useful?

Characters remaining:

Feedback Message