V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

12.5.1. General Options Parameters for Deterministic Latency PHY

This section describes how to set basic parameters of your transceiver PHY for the Deterministic Latency PHY IP core using the general options tab.

Use the General Options tab to set your basic device parameter settings.

Table 166.  General Options
Name Value Description
Device family Arria V, Cyclone V, Stratix V Specifies the device family. Arria V, Cyclone V, and Stratix V are available.
Mode of operation Duplex, TX, RX You can select to transmit data, receive data, or both.
Number of lanes 1-32 The total number of lanes in each direction.
FPGA fabric transceiver interface width 8, 10, 16, 20, 32, 40 Specifies the word size between the FPGA fabric and PCS. Refer to Sample Channel Width Options for Supported Serial Data Rates for the data rates supported at each word size.
PCS‑PMA interface width 10, 20 Specifies the datapath width between the transceiver PCS and PMA. A deserializer in the PMA receives serial input data from the RX buffer using the high-speed recovered clock and deserializes it using the low‑speed parallel recovered clock.
PLL type CMU, ATX Specifies the PLL type. The CMU PLL has a larger frequency range than the ATX PLL. The ATX PLL is designed to improve jitter performance and achieves lower channel-to-channel skew; however, it supports a narrower range of data rates and reference clock frequencies. Another advantage of the ATX PLL is that it does not use a transceiver channel, while the CMU PLL does. Because the CMU PLL is more versatile, it is specified as the default setting.
Data rate Device Dependent If you select a data rate that is not supported by the configuration you have specified, the MegaWizard displays a error message in the message pane. Sample Channel Width Options for Supported Serial Data Rates for sample the channel widths that support these data rates.
Base data rate

1 × Data rate

2 × Data rate

4 × Data rate

8 × Data rate

For systems that transmit and receive data at more than one data rate, select a base data rate that minimizes the number of PLLs required to generate the clocks for data transmission. The Recommended Base Data Rate and Clock Divisors for CPRI table lists the recommended Base data rates for various Data rates.

The available options are dynamically computed based on the Data rate you specified as long as those Base data rates are within the frequency range of the PLL.

Input clock frequency

Data rate/20

Data rate/10

Data rate/8

Data rate/5

Data rate/4

Data rate/2.5

Data rate/2

Data rate/1.25

Data rate/1

This is the reference clock for the PHY PLL. The available options are based on the Base data rate specified.
Enable tx_clkout feedback path for TX PLL On/ Off When On, the core uses TX PLL feedback to align the TX core clock with the source to the TX PLL which is the RX recovered clock. This configuration is shown in Using TX PLL Feedback to Align the TX Core Clock with the RX Core Clock.

The following table lists the available channel widths available at selected frequencies. The channel width options are restricted by the following maximum FPGA-PCS fabric interface frequencies:

  • Arria V devices—153.6 MHz
  • Cyclone V devices—153.6 MHz
  • Stratix V devices—221 MHz
Table 167.  Sample Channel Width Options for Supported Serial Data Rates
Serial Data Rate (Mbps) Channel Width (FPGA-PCS Fabric)
Single-Width Double-Width
8-Bit 16-Bit 16-Bit 32-Bit
614.4 Yes Yes No No
1228.8 Yes Yes Yes Yes
2457.6 No Yes Yes Yes
3072 No Yes Yes Yes
4915.2 No No No Yes
6144 No No No Yes

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