V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

16.6.6. Word Aligner and BitSlip Parameters

The word aligner aligns the data coming from RX PMA deserializer to a given word boundary. When the word aligner operates in bitslip mode, the word aligner slips a single bit for every rising edge of the bit slip control signal.
Note: For more information refer to the Word Aligner section in the Transceiver Architecture inCycloneV Devices.
Table 308.  Word Aligner and BitSlip Parameters 

Parameter

Range

Description

Enable TX bit slip

On/Off

When you turn this option On, the PCS includes the bitslip function. The outgoing TX data can be slipped by the number of bits specified by the tx_bitslipboundarysel control signal.

Enable tx_std_bitslipboundarysel control input port.

On/Off

When you turn this option On, the PCS includes the optional tx_std_bitslipboundarysel control input port.

RX word aligner mode

bit_slip

sync_sm

Manual

Specifies one of the following 3 modes for the word aligner:

  • bit_slip: You can use bit slip mode to shift the word boundary. For every rising edge of the rx_bitslip signal, the word boundary is shifted by 1 bit. Each bitslip removes the earliest received bit from the received data.
  • sync_sm: In synchronous state machine mode, a programmable state machine controls word alignment. You can only use this mode with 8B/10B encoding. The data width at the word aligner can be 10 or 20 bits. When you select this word aligner mode, the synchronous state machine has hysteresis that is compatible with XAUI. However, when you select cpri for the Standard PCS Protocol Mode, this option selects the deterministic latency word aligner mode.
  • Manual: This mode enables word alignment by asserting the rx_std_wa_pattern. This is an edge sensitive signal.

RX word aligner pattern length

7, 8, 10, 16, 20, 32, 40

Specifies the length of the pattern the word aligner uses for alignment. The pattern is specified in LSBtoMSB order.

RX word aligner pattern (hex)

User-specified

Specifies the word aligner pattern in hex.

Number of word alignment patterns to achieve sync

1–256

Specifies the number of valid word alignment patterns that must be received before the word aligner achieves synchronization lock. The default is 3.

Number of invalid words to lose sync

1–256

Specifies the number of invalid data codes or disparity errors that must be received before the word aligner loses synchronization. The default is 3.

Number of valid data words to decrement error count

1–256

Specifies the number of valid data codes that must be received to decrement the error counter. If the word aligner receives enough valid data codes to decrement the error count to 0, the word aligner returns to synchronization lock.

Run length detector word count

0–63

Specifies the maximum number of contiguous 0s or 1s in the data stream before the word aligner reports a run length violation.

Enable rx_std_wa_patternalign port

On/Off

Enables the optional rx_std_wa_patternalign control input port.

Enable rx_std_wa_a1a2size port

On/Off

Enables the optional rx_std_wa_a1a2size control input port.

Enable rx_std_bitslipboundarysel port

On/Off

Enables the optional rx_std_wa_bitslipboundarysel status output port.

Enable rx_std_bitslip port

On/Off

Enables the optional rx_std_wa_bitslip control input port.

Enable rx_std_runlength_err port

On/Off

Enables the optional rx_std_wa_runlength_err control input port.

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