9. PHY IP Core for PCI Express (PIPE)
The Gen1 and Gen2 datapaths are compliant to the Intel PHY I nterface for PCI Express (PIPE) Architecture PCI Express 2.0 specification. The Gen3 datapath is compliant to the PHY Interface for the PCI Express Architecture PCI Express 3.0 specification. You must connect this PHY IP Core for PCI Express to a third-party PHY MAC to create a complete PCI Express design.
The PHY IP Core for PCI Express supports ×1, ×2, ×4, or ×8 operation for a total aggregate bandwidth ranging from 2 to 64 Gbps. In Gen1 and Gen2 modes, the PCI Express protocol uses 8B/10B encoding which has a 20% overhead. Gen3 modes uses 128b/130b encoding which has an overhead of less than 1%. The Gen3 PHY initially trains to L0 at the Gen1 data rate using 8B/10B encoding. When the data rate changes to Gen3, the link changes to 128b/130b encoding.
Altera also provides a complete hard IP solution for PCI Express that includes the Transaction, Data Link and PHY MAC. For more information about Altera’s complete hard IP solution, refer to the Stratix V Hard IP for PCI Express IP Core User Guide.
Figure 47 illustrates the top-level blocks of the Gen3 PCI Express PHY (PIPE) for Stratix V GX devices. Figure 48 illustrates the top-level blocks of the Gen1 and Gen2 IP cores. As these figures illustrate, the PIPE interface connects to a third-party MAC PHY implemented using soft logic in the FPGA fabric. The reconfiguration buses connect to the Transceiver Reconfiguration Controller IP Core. For more information about this component, refer to Transceiver Reconfiguration Controller IP Core. An embedded processor connects to an Avalon-MM PHY management interface for control and status updates.
For more detailed information about the PCI Express PHY PIPE transceiver channel datapath, clocking, and channel placement, refer to the “PCI Express” section in the in the Transceiver Configurations in Arria V GZ Devices or Transceiver Configurations in Stratix V Devices as appropriate.
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