V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

5.3. 1G/10GbE PHY Performance and Resource Utilization

This topic provides performance and resource utilization for the IP core in Arria V GZ and Stratix V devices.

The following table shows the typical expected resource utilization for selected configurations using the current version of the Intel® Quartus® Prime software targeting a Stratix V GT (5SGTMC7K2F40C2) device. The numbers of ALMs and logic registers are rounded up to the nearest 100. Resource utilization numbers reflect changes to the resource utilization reporting starting in the Quartus II software v12.1 release 28 nm device families and upcoming device families.

Table 49.  1G/10 GbE PHY Performance and Resource Utilization
PHY Module Options ALMs M20K Memory Logic Registers
1GbE/10GbE - 1GbE only 300 0 600
1GbE/10GbE - 1GbE only with Sequencer 400 0 700
1GbE/10GbE - 1GbE/10GbE with 1588 1000 4 2000
1GbE/10GbE - 1GbE/10GbE with 1588 and Sequencer 1100 4 2000

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