V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

10.3.5. Byte Order Parameters

The byte ordering block is available when the PCS width is doubled at the byte deserializer. Byte ordering identifies the first byte of a packet by determining whether the programmed start-of-packet (SOP) pattern is present; it inserts enough pad characters in the data stream to force the SOP to the lowest order byte lane.
Note: You cannot enable Rate Match FIFO when your application requires byte ordering. Because the rate match function inserts and deletes idle characters, it may shift the SOP to a different byte lane.
Table 130.  Byte Order Options
Name Value Description
Enable byte ordering block On/Off Turn this option on if your application uses serialization to create a datapath that is larger than 1 symbol. This option is only available if you use the byte deserializer for the following configurations:
  • Configuration 1:
    • 16-bit FPGA fabric-transceiver interface
    • No 8B/10B decoder (8-bit PMA-PCS interface)
    • Word aligner in manual alignment mode
  • Configuration 2:
    • 16-bit FPGA fabric-transceiver interface
    • 8B/10B decoder (10-bit PMA-PCS interface)
    • Word aligner in automatic synchronization state machine mode
  • Configuration 3:
    • 32-bit FPGA fabric-transceiver interface
    • No 8B/10B decoder (16-bit PMA-PCS interface)
    • Word aligner in manual alignment mode
  • Configuration 4:
    • 32-bit FPGA fabric-transceiver interface
    • 8B/10B decoder (20-bit PMA-PCS interface)
    • Word aligner in manual alignment mode
  • Configuration 5:
    • 40-bit FPGA fabric-transceiver interface
    • No 8B/10B decoder (20-bit PMA-PCS interface)
    • Word aligner in manual alignment mode
This option creates the rx_byteordflag signal which is asserted when the received data is aligned to the byte order pattern that you specified.
Enable byte ordering block manual control On/Off Turn this option on to choose manual control of byte ordering. This option creates the rx_enabyteord signal. A byte ordering operation occurs whenever rx_enabyteord is asserted. To perform multiple byte ordering operations, deassert and reassert rx_enabyteord.
Byte ordering pattern Depends on configuration Specifies the pattern that identifies the SOP. For 16-bit byte ordering pattern you must include a 2-bit pad so that the pattern entered is in the following format: 00 <pattern> 00 <pattern>. For example, if the required pattern is 10111100, enter the following pattern: 00101111000010111100

Enter the byte ordering pattern as follows based on the 5 configurations that support byte ordering as described in the Enable byte ordering block:

  • Configuration 1: 8-bits
  • Configuration 2: 10-bits

    For example: If you select a /Kx.y/ control code group as the byte ordering pattern, the most significant 2 bits of the 10-bit byte ordering pattern must be 2'b01. If you select a /Dx.y/ data code group as the byte ordering pattern, the most significant 2-bits of the 10-bit byte ordering pattern must be 2'b00. The least significant 8-bits must be the 8B/10B decoded version of the code group used for byte ordering.

  • Configuration 3:16-bits, 8-bits
  • Configuration 4: 18-bits
  • Configuration 5: 20-bits, 10-bits

    For example: If you select a /Kx.y/Dx.y/ code group as the byte ordering pattern, the most significant 2-bits of the 20-bit byte ordering pattern must be 2'b01. Similarly bit[9:0] must be 2'b00. Bit[18:10] must be the 8B/10B decoded version of /Kx.y/. Bit[7:0] must be 8B/10B decoded version of /Dx.y/.

Byte ordering pad pattern 00000000 Specifies the pad pattern that is inserted to align the SOP. Enter the following size pad patterns:
Data Width 8B/10B Encoded?  Pad Pattern
8, 16, 32   No 8 bits
10, 20, 40 No 10 bits
8, 16, 3 No 9 bits

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