V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

9.12. PHY for PCIe (PIPE) Register Interface and Register Descriptions

The Avalon-MM PHY management interface provides access to the PHY IP Core for PCI Express PCS and PMA features that are not part of the standard PIPE interface. You can use an embedded controller acting as an Avalon-MM master to send read and write commands to this Avalon-MM slave interface.

The following figure provides a high-level view of this hardware; modules shown in white are hard logic and modules shown in gray are soft logic.

Figure 51. PCI Express PIPE IP Core Top-Level Modules
Table 119.  Avalon-MM PHY Management Interface
Signal Name Direction Description
phy_mgmt_clk Input

Avalon-MM clock input.

There is no frequency restriction for Stratix V devices; however, if you plan to use the same clock for the PHY management interface and transceiver reconfiguration, you must restrict the frequency range of phy_mgmt_clk to 100-125 MHz to meet the specification for the transceiver reconfiguration clock.

phy_mgmt_clk_reset Input Global reset signal that resets the entire PHY IP core. This signal is active high and level sensitive.
phy_mgmt_address[8:0] Input 9-bit Avalon-MM address.
phy_mgmt_writedata[31:0] Input Input data.
phy_mgmt_readdata[31:0] Output Output data.
phy_mgmt_write Input Write signal.
phy_mgmt_read Input Read signal.
phy_mgmt_waitrequest Output When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request. When asserted, control signals to the Avalon-MM slave interface must remain constant.

PHY for PCIe (PIPE) Register Interface and Register Descriptions describes the registers that you can access over the Avalon-MM PHY management interface using word addresses and a 32-bit embedded processor. A single address space provides access to all registers.

Note: Writing to reserved or undefined register addresses may have undefined side effects.
Table 120.  PCI Express PHY (PIPE) IP Core Registers
Word Addr Bits R/W Register Name Description
PMA Common Control and Status Registers
0x022 [31:0] R pma_tx_pll_is_locked Bit[P] indicates that the TX CMU PLL (P) is locked to the input reference clock. There is typically one pma_tx_pll_is_locked bit per system.
Reset Control Registers–Automatic Reset Controller
0x041 [31:0] RW reset_ch_bitmask

Reset controller channel bitmask for digital resets. The default value is all 1s. Channel <n> can be reset when

bit<n> = 1.

0x042 [1:0] W reset_control (write)

Writing a 1 to bit 0 initiates a TX digital reset using the reset controller module. The reset affects channels enabled in the reset_ch_bitmask. Writing a 1 to bit 1 initiates a RX digital reset of channels enabled in the reset_ch_bitmask.

Refer to Timing Constraints for Reset Signals when Using Bonded PCS Channels for a SDC constraint you must include in your design.

R reset_status (read) Reading bit 0 returns the status of the reset controller TX ready bit. Reading bit 1 returns the status of the reset controller RX ready bit.
Reset Controls –Manual Mode
0x044 [31:0] RW reset_fine_control

You can use the reset_fine_control register to create your own reset sequence. The reset control module, illustrated in Transceiver PHY Top-Level Modules, performs a standard reset sequence at power on and whenever the phy_mgmt_clk_reset is asserted. Bits [31:4, 0] are reserved.

[31:4] RW Reserved It is safe to write 0s to reserved bits.
[3] RW reset_rx_digital Writing a 1 causes the RX digital reset signal to be asserted, resetting the RX digital channels enabled in reset_ch_bitmask. You must write a 0 to clear the reset condition.
[2] RW reset_rx_analog Writing a 1 causes the internal RX digital reset signal to be asserted, resetting the RX analog logic of all channels enabled in reset_ch_bitmask. You must write a 0 to clear the reset condition.
[1] RW reset_tx_digital

Writing a 1 causes the internal TX digital reset signal to be asserted, resetting all channels enabled in reset_ch_bitmask. You must write a 0 to clear the reset condition.

Refer to Timing Constraints for Reset Signals when Using Bonded PCS Channels for a SDC constraint you must include in your design.

[0] RW pll_powerdown Writing a 1 causes the internal TX PLL to powerdown. If you reset the transceiver, you must assert pll_powerdown by writing a 1 to this register and then writing a 0 after 1 ms.
PMA Control and Status Registers
0x061 [31:0] RW phy_serial_loopback Writing a 1 to channel <n> puts channel <n> in serial loopback mode.
0x063 [31:0] R pma_rx_signaldetect When channel <n> =1, indicates that receive circuit for channel <n> senses the specified voltage exists at the RX input buffer. This option is only operational for the PCI Express PHY IP Core.
0x064 [31:0] RW pma_rx_set_locktodata When set, programs the RX CDR PLL to lock to the incoming data. Bit <n> corresponds to channel <n>.
0x065 [31:0] RW pma_rx_set_locktoref When set, programs the RX CDR PLL to lock to the reference clock. Bit <n> corresponds to channel <n>.
0x066 [31:0] R pma_rx_is_lockedtodata When asserted, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to LTD mode. Bit <n> corresponds to channel <n>.
0x067 [31:0] R pma_rx_is_lockedtoref When asserted, indicates that the RX CDR PLL is locked to the reference clock. Bit <n> corresponds to channel <n>.
PCS for PCI Express
0x080 [31:0] RW Lane or group number Specifies lane or group number for indirect addressing, which is used for all PCS control and status registers. For variants that stripe data across multiple lanes, this is the logical group number. For non-bonded applications, this is the logical lane number.
0x081 [31:6] R Reserved
[5:1] R rx_bitslipboundaryselectout

Records the number of bits slipped by the RX Word Aligner to achieve word alignment. Used for very latency sensitive protocols.

From block: Word aligner.

[0] R rx_phase_comp_fifo_error

When set, indicates an RX phase compensation FIFO error.

From block: RX phase compensation FIFO.

0x082 [31:1] R Reserved
[0] RW tx_phase_comp_fifo_error

When set, indicates a TX phase compensation FIFO error.

From block: TX phase compensation FIFO.

0x083 [31:6] RW Reserved
[5:1] RW tx_bitslipboundary_select

Sets the number of bits the TX block needs to slip the output. Used for very latency sensitive protocols.

From block: TX bit-slipper.

0x084 [31:1] RW Reserved
0x085 [31:4] RW Reserved
[3] RW rx_bitslip

When set, the word alignment logic operates in bitslip mode. Every time this register transitions from 0 to 1, the RX data slips a single bit.

From block: Word aligner.

[2] RW rx_bytereversal_enable

When set, enables byte reversal on the RX interface.

From block: Word aligner.

[1] RW rx_bitreversal_enable

When set, enables bit reversal on the RX interface.

From blockk: Word aligner.

[0] RW rx_enapatternalign

When set, the word alignment logic operates in pattern detect mode.

From block: Word aligner.

0x086 [31:20] R Reserved
[19:16] R rx_rlv

When set, indicates a run length violation.

From block: Word aligner.

[15:12] R rx_patterndetect

When set, indicates that RX word aligner has achieved synchronization.

From block: Word aligner.

[11:8] R rx_disperr

When set, indicates that the received 10-bit code or data group has a disparity error. When set, the corresponding errdetect bits are also set.

From block: 8B/10B decoder.

[7:4] R rx_syncstatus

When set, indicates that the RX interface is synchronized to the incoming data.

From block: Word aligner.

[3:0] R rx_errdetect

When set, indicates that a received 10-bit code group has an 8B/10B code violation or disparity error. It is used along with RX disparity to differentiate between a code violation error and a disparity error, or both.

In PIPE mode, the PIPE specific output port called pipe_rxstatus encodes the errors.

From block: 8B/10B decoder.

For more information about the individual PCS blocks, refer to Transceiver Architecture in Stratix V Devices in the Stratix V Device Handbook.

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